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Recent content by gilazilla

  1. G

    Question about stretching data for 2 clock cycle

    Hi All, I have a question about clocking. I want to achieve "result 2".(see attachment) However i am having problem getting the correct system verilog to work. I have no idea why it did not as expected. I keep on getting result 1 :( Need some advice here.Thanks. Each character is 5ns wide...
  2. G

    Question about 2x clocking

    Hi All, I have a question about clocking. I want to achieve "result 2".(see attachment) However i am having problem getting the correct system verilog to work. I have no idea why it did not as expected. I keep on getting result 1 :( Need some advice here.Thanks. Each character is...
  3. G

    Change bus signal to bit signal in EVCD

    Hi , I am a newbie here. Do you anyone know how to do this.Any script out there? Original EVCD. $var port [3:0] <11 a $end This is what i want. $var port 1 <11 a [0] $end $var port 1 <12 a [1] $end $var port 1 <13 a [2] $end $var port 1 <14 a [3] $end And of course after the...
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