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When I was reading the datasheet,I have a question about the datasheet.
at the page 7 of the datasheet, promises a throughput rate of 117 kHz as below.
But when I calcalate the read time referring to the photo below,it turns to be (16.5 *1/8.33MHz=1.98us),for the rising edge of the SCLK should...
Hi，
exactly,there is a engineer whose job is to design the schematic and pcb layout.So,until now,I don't know the hardware detail or if the engineer will do well.Last time,you said we should use 48 ohm to avoid reflection.Our manager said we will use 22 ohm resistor.
1606469421
Thanks,what I...
Hi,
oh,maybe,I made a mistake.
Last time,you asked me to post the datasheet of the FPGA used in the project for guarentee.So,I posted the paper.And,I don't to know if it will work stably and how to analyse.
Actually,the last company I worked in requested that we had to work from 8:30 AM to 9 PM for 3 days and from 8:30 AM to 5:30 PM for 3 days in a week.Even when I was ready to sleep at 11 or 12 PM,the manager could call me to talk about work.Work can be pushing,and pressure was very large.So,I...
Hi
Actually,I don't have the schematic either because our engineer hasn't drawn it,but I can draw it by myself.
Following is the schematic.We configure the four ADCs together.
I have no knowledge in this area.Can you tell me more detail about it.?
Hi
I see Vol is 0.4V and Voh is (vcco - 0.4v=2.9v)
What I want is guarantee but not guessing,so,please tell me more about it.I am eager to know more.
Following is the datasheet of FPGA.The device is gw1n-4.
The requirement is:
1)4 ADCs work together in the same mode configured also in the...
Thanks for your help.Sorry for that I haven't shown the detail while asking the question.I'm really a freshman in this area,and I have tried my best to do it well.But,in my circumstance,nobody has the knowledge.So I ask the question here.Following is the details.The ADC is LTC1867L.
1) because...
Hello,everyone.Recently,I'm working on a project with 4 ADC chips.I need to use FPGA to control 4 ADC chips synchronously with CS、SDI、SCK signals.But now,I don't know whether the pin from FPGA can drive 4 pins from ADCs and the SPI bus can work stably.Do I need to add a pull up resistor to the...
Hi
In fact,I have spent much money and time on FPGA.What I want to say is that self-study can be very difficuit for a freshman in this field ,and he or her ,at the same time has a urging work to do.In our country,designing is a very fast thing that self-study can't cover the necessary...
Hi
Perhaps,I'm too lazy and want to make few efforts to get more knowledge or finish the work.But,at the same time,work can be urgent and I don't know the proper learning order and don't have enough time.These are big problems when one graduate from university 、is not very familar with FPGA and...
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