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I see some of the mistakes I have made in writing this. Thank you everyone. I will try and fix those!
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Nah,
I am trying to write a hex vector in input for a system which can only take binary bits as inputs. I want to define a box in verilog which will take a hex input from...
I have ABSOLUTELY no background in verilog (or digital designs for that matter). Just for ease of simulations of larger analog systems, I thought it would be better to provide hex inputs instead of long chains of binary values. So I decided to write veriloga code that spectre can understand. I...
Hello all,
I am performing Monte Carlo using ADExL for mismatch analysis in one schematic. The schematic has a bunch of instances instantiated by iterations. (For example, R<2:0> to indicate 3 R in series/parallel). When I select the instances to be mismatched, Cadence says that the iterated...
Got it. First evaluate, or simply write equation for gain (not dB) i.e., Vout/Vin, and then use PhaseMargin function on the value/equation in buffer. Dont forget to ADD 180 to the answer received.
Hello,
Can anyone tell me how to use the function phaseMargin in the cadence Analog environment calculator?
When i try to compute the Phase margin manually and compare it with cadence calculator, it doesnt match. the calculator number seems completely realistic. Can anyone tell me how to use it?
A quick update. it looks like i was not using statistical variation models for that. then i changed the model files and did it again. now this time i am using models with statistical variation. however, it runs pretty well in Nominal corner, but when i simulate other corners like SS/FF -...
Hey all,
is there any gizmo that we can use to convert a non-dlna TV into DLNA? Apparently the DLNA TVs are damn expensive and if you can buy a DLNA chip and figure out a way to attach with then this should be easy + Exciting! isnt it?
Anyone interested in helping me with the experiment?
Hello all,
Help needed in Monte Carlo
I am using Cadence 6.1 Virtuoso for my analysis.
I followed the help of ADExL and tried to run Monte Carlo following the steps provided. I am able to run the simulation, but it doesn’t seem to be giving results. These are the steps I follow,
1. Setting...
Dear all,
I am working on a design of a voltage regulator which involves using a diffpair in a closed loop.
However- at low load current the phase margin sucks and the gain is in negative, but to my surprise, it still works in transient analysis. How can this be possible? whats going on?
Any...
Oveis,
The amount of variation is something you should try to seek from the industry. The professor with whom i was working got me some data from industry. dont know whether there is any other way to do so or not,. I am sure there must be a way out of it.
Dear Oveis,
use some perl scripts to perform some text manipulation and replace all VDD_dummyxx with VDD and same for VSS.
unfortunately using v2s command by hsim has a con- about the supply rail names.
But running through perl script is really easy and should solve this problem.
not sure if understood correctly... you want to provide input to the diffpair? or do you want to bias the diff pair?
for common mode voltage, you can use the AC voltage source and it also has a parameter named 'DC level'. if you specify that DC level, then the AC will be mounted on that DC...
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