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I'm using TSMC std lib cells (I believe their layers are standardized and shouldn't elicit such DRV, isn't is so?). Is there a way to solve this problem? Do I need to add a marker layer somehow to indicate high voltage to pass this DRC?
What is an HiR resistor in the context of the violation?
I have a placed and routed design in Innovus, from which I extracted an .OAS file - I ran Calibre for DRC and the following violation popped up for std cells as well as filler/dcap cells in my design. At first I though this has something to do with the tap cells, but the description doesn't...
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