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Yes we are working off different datasheets.
What caught my eye was phase margin graph at G = 5 of 71 degrees, implied, but not directly stated for the
graph, Cload of 1000 pF as discussed in datasheet but no test circuit shown, so what was Cload on graph,
what parasitics used in fdbk...
For sure their datasheet for large signal response shows non linear slew rate limiting.
Their phase margin at G = 5 implies the numerical value of 71 degrees aligns
with below measured ss response.
Sooo what is the phase margin at G < 5.....sloppy datasheet, given the G=5 phase
margin pretty high.
Actually I could not find a hard stop for G = 1, just a reference, with large Cload,
thats its unstable < G = 5. They do call out -
But doing a sim, with a 1V step, riding on step final value is a high freq osc, no Cload.
And datasheet G and Phase, does not extend to G = 1, maybe the author...
DC sweep close to crossover (w/o diodes one can observe the xcrossover) :
Small sig analysis
Zout seems constrained to ~ .1 mOhm at peak. Seems low to me, again how good
is the model.....not you have to subtract .1 ohms from curve due to method I used
to get at it.
Not sure about OP37...
https://www.courses.ece.vt.edu/ece3274/poweramp.pdf
https://www.ti.com/content/dam/videos/external-videos/en-us/1/3816841626001/4650731413001.mp4/subassets/output-stage-presentation.pdf
https://link.springer.com/article/10.1007/s10470-006-5371-6
Sometimes you can get authors to send you...
A discussion of protocol and interface :
https://smartfarm.rmuti.net/download/14serialcommunication.pdf
Search on youtube for "esp8266 to arduino serial link", quite a few videos.
As betwixt points out a UART sends data, byte at a time, and the UART does
not know what the bytes are or their...
https://www.ti.com/lit/ug/tiduaa8/tiduaa8.pdf?ts=1666319019907
https://www.ti.com/content/dam/videos/external-videos/en-us/9/3816841626001/6308652805112.mp4/subassets/interfacing_with_quadrature_encoders_-_updated.pdf
Tons of videos on youtube.
Todays processors typically have a quaddec...
Your original post file attached implied circuit was for 72V detection, where were you
going to sense the 72V in the circuit ?
Note the attached file, a RAR archive, my RAR utility says its corrupted....
Keep in mind cap ESR of course matters, polymer Tant best for bulk,
ceramic additionally helps with high freq stuff. The OS-CON below is the
poly Tant.
And of course C lead length L and trace L aggravate the problem.
An example of simple server app on an ESP8266, noise due largely to xmit activity.
As you can see we easily get 200+ mV rail drops. This is with additional bulk C 10 uF, tant
on main board module plugged into. What you are seeing is 3.3V reg on module, and part
also driving, typically, one...
I understand .. but with 56R in series with the gate capacitance of 1800 pF (not counting gobs of
Miller) .....
1744916737
The answer to this is rather than guessing at values sim the circuit and
play with values for feedback to sim user. Obviously include parasitics
for a more complete sim.
Or...
I expect stability problems when looking into a MOSFET gate with 1800 pF not counting
aggravating miller load, thru a real low R and manufacturer curves telling me my phase
margin is around 25 degrees (not counting miller). And an OpAmp datasheet speced
mainly at 10 pF load.......
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