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can you please share some DSP interview questions for Cadence Design Systems USA? the position for which i am going to interview is Intern ( encoding/DSP/High Speed Simulation/Algorithmic Modeling (AMI)/IBIS)
i have to send a 32bit input (IP address in hex for eg 703020F8 ). I need to take 4bits at a time and perform some operation on it,then next 4bits and so on.. how do i do it in verilog?
in gate level, I take 32bits,put it through a 32bit register, take an output of 8 lines (4bits each) and then...
i have a 32bit IP address in hex..say 703020F8..i have to extract first 4bits(in binary) ,do some operation with it, then extract next 4bits and so on..how do i do it? i m a beginner so this question might sound silly.. plz help!
Re: design of counters..
thanks for your reply.. yes i can do that but then, what do the values start and overflow signify? i dont understand what they mean and where to use them.
hi ppl!
can u plz tell me how to solve this question..
Please design a counter that counts the number of times the
number “5” appears in an 4-bit input stream. The I/O are as follows:
NumberIn : 4-bits wide (input)
Start: Reset counter and overflow flag to zero while start is high (input)...
This is a design question. Please design a counter that counts the number of times the
number “5†appears in an 4-bit input stream. The I/O are as follows:
NumberIn : 4-bits wide (input)
Start: Reset counter and overflow flag to zero while start is high (input)
Count: 8-bit...
the conditions given are:
NumberIn : 4-bits wide (input)
Start: Reset counter and overflow flag to zero while start is high (input)
Count: 8-bit unsigned count (of the number of “5â€s that have occurred since start went
low (output)
Overflow: Goes high if count overflows (count is...
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