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Recent content by CatKing

  1. C

    First Encounter back end

    yes, it's only for stream out merging
  2. C

    stream in from encounter to virtuoso

    eaasy way: save OA design and use icfb with OA support if you want uses gds, map file is very important, try let encounter create streamOut.map at 1st time, then modify by your hand, you must know which layer of encounter will translate into the layer of gds. you can to read the tech section...
  3. C

    this VIOLATION?????????

    it's HFN, so set it as ideal net in DC, let APR tool handle it as cdic says.
  4. C

    Cadence encounter 2 metal layer problem

    for .5 process, 3M better. because 1st metal always used by cell layout, most of these areas are not available for routing, but for success routing, you need at lease 2 layers, M2 for horizontal routing and M3 for vertical. so the 3M is the better choice for APR, 2M better for hand craft layout.
  5. C

    Estimate gate count in Verilog?

    no, they are different, for a .5um preocess example: MACRO ND02D1 SIZE 5.40 BY 16.20 ; ... MACRO ND02D2 SIZE 10.80 BY 16.20 ; ... because more drive strength need more W/L ratio of MOSFETs, when W increases. cell area will increases.
  6. C

    Hardware IP/UDP stack?

    udp ip xilinx some korea company had made it, but i forgot the name, maybe netwiz or else.
  7. C

    Is the ACS command of DC used in your company?

    ACS needs lots of cpus, otherwise it's no value, because it's "distrubuted synthesis", the acs engine partition big design into small pieces, and synthesis them concurrently in many cpus, that's why it can handle large designs and improve runtime.
  8. C

    Are you satisfied with design service/ASIC house's die size

    Re: Are you satisfied with design service/ASIC house's die s in the case of low metal layer used(2-4 Layer), and the scale is large(gatecount > 300K), the chip utilization will be as low as 50 %, otherwise the routebility will not be reached. another issue is pad limit, if you have too much...
  9. C

    RTL Encounter VS Design Compiler

    it's true, the same case as synplify vs fpga compiler, but, the dc is the industrial standard now, it's the only problem to replace it with other asic synthesis tools.
  10. C

    What files do I need to run SE ?(the same as in Apollo?)

    Re: SE or Apollo but doc only, no tutorial files.
  11. C

    The advantages of using MAGMA for ASIC

    Re: ASIC with MAGMA Check Magma WhitePapers: **broken link removed**
  12. C

    Size of a NAND gate in 0.18 micron technology

    10.x um^2 (5.0x * 1.9x)in tsmc/umc/csm/smic .18 technology
  13. C

    What files do I need to run SE ?(the same as in Apollo?)

    SE or Apollo no skill needed, just look for some salple .mac (macro) files in se docs.
  14. C

    Help:Using more than one nios in the FPGA

    avalon switch fabric supports multi nios core as bus master.
  15. C

    Looking for documents about H.264 implementation on a DSP

    H.264 on a DSP, help 1. uses powerful dsp(perfered with multimedia accelarator, e.g. TI DM642) 2. assemble code can get more perferemce than c code.
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