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Recent content by brahmi15

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    SPI communication between FPGA(as a slave) and microcontroller(as master)

    Xilinx provides the SPI driver and there is one slave polled mode example. which is by default working as a slave.
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    SPI communication between FPGA(as a slave) and microcontroller(as master)

    Hello @KlausST Thank you for your reply. master (microcontroller) which send the 0x55 data continues when chip select is low.
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    SPI communication between FPGA(as a slave) and microcontroller(as master)

    Hello all, I am using ZC-706 zynq board as slave and atmega128 microcontroller as master. I want to do spi communication between them. For testing i am just transmitting 1 byte of data which is transmitting successfully from the master side. For FPGA slave i am using AXI quad spi IP core...
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Hello ads-ee, Thank you for your reply. Kindly find the below pin configuration of my code. module lvds_to_single_ended( input rx_clk_in_p, // data_clk_p input rx_clk_in_n, // data_clk_n input rx_frame_in_p, input rx_frame_in_n, input [ 5:0] rx_data_in_p, input [ 5:0] rx_data_in_n, output...
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Hi ads-ee, Thank you for your reply. I want to connect an LVDS input to an LVTTL output . Please guide with an example how should I do it?
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Hi, Kindly find the attached link which i referred. http://zedboard.org/sites/default/files/documentations/PicoZed%20SDR%202x2%20SOM%20User's%20Guide%20v1.7_0.pdf http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf module Lvds_io ( input wire RX0_P...
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Yes i read the mentioned help/documentation but i didn't get exact idea. kindly help.
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Every pins i need to define?
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Hello Klaus, Thank you for your reply. I see that the ADRV9361-Z7035 uses the Xilinx XC7Z035-L2 FBG676I. From UG865 we find that banks 12 and 13 of the Z7035 are PL-side HR banks. We are using vivado design suite 2018.3 and verilog language. From the ADRV9361-z7035 both are using LVDS...
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    how to do LVDS to LVTTL signal conversion in FPGA?

    Hello, I am new FPGA. And yes we are using bank 12 and bank 13 which are PL-side HR banks. From the ADRV9361-z7035 both are using LVDS conversion and it goes into the bank 35. We have to route the signal from Bank 35 to bank 12 or 13 to connect external device for that we want to do LVDS to...
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