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Hi, I am testing a verilog code which has the following structure:
reg a;
wire b;
always @(posedge clk) begin a <= b; end
wire c = a ^ 1 ;
assign b = c ^ 1 ;
But all a, b and c are coming as undefined in the behavioral simulation. This is a part of a bigger code, after debugging the signals...
Hi,
Thank you for answering.
I double checked and the sdc file is correctly read by Innovus. And replacing "create_clock_tree_spec" with place_opt also does not work. ccopt_design is facing the same errors.
Hi everyone,
I am trying to implement ccopt_design in Innovus (version 22.1) and facing a cople of errors which I am not understanding enough what is the error about. The error are:
1. **ERROR: (IMPCCOPT-4082): No timing clocks found therefore cannot extract clock trees. An SDC file...
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