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What about the other side? does the clk freq has a set relationship with the source or not？and how many bits the other side take each time?
I agree with Barry, sounds like a fifo solution..
I am having difficulties running a test with assertion enabled within a certain hierarchy. The test runs smoothly while I disable the assertion using command
PLUS_ARG += kr_global_disable_all_asserts
in Makefile. However, when I use a command file enable assertion under a certain...
There are different scenarios for when the clock frequency is slower than or faster than your source clk freq.
have one solution for all scenarios are tough. I remember I did some latch mechanism for handshakes between two clock domain. it is not a simple async fifo solution, especially fifo...
It really depends on 1, the clock frequency different between the wrclk and rdclk, 2, package size ( meaningful data length between idles).
There are two extreme scenarios
1， with clock frequency difference to be infinity big ( one clock with f=0, and the other one is f=infinity), then no...
Hi ,
I am using UVM 1.0 from Accellera and VCS vcs-mx-E-2011.03.
In my sequence, I have the following syntax
assert(req.randomize(clkgen) with {clock.period ==m_period ;});
However, I see print out m_period is correct ( a non zero number) but clock.period in item req is zero.
I have a...
Thanks siskin!
This is what I did...
I found a library directory from the pool, and add a VSIM_OPT += -L {LIB_PATH}
I saw modelsim picked up the lib, but i then got a fatal error complaining about the lib is outdated... That's because the lib is compiled using an older version of modelsim...
Dear All,
I was trying to get a gate sim running in my environment. There are components from TSMC library in the Gate level netlist that I need to include to the compile file. We use compile.xml as compile spec for all design/test file for makefile to pick up during compile stage. However, i...
Dear All,
I was trying to get a gate sim running in my environment. There are components from TSMC library in the Gate level netlist that I need to include to the compile file. We use compile.xml as compile spec for all design/test file for makefile to pick up during compile stage. However...
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