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Recent content by atulkulkarni

  1. A

    Unable to create symbol in veriloga

    I am unbale to create symbol in veriloga after clicking on save button as the tool doesnt even ask. Also when I look into the parser file there are no errors but when I try to close the file it throws syntax errors but not the line numbers. The code I am trying to run has not errors as it is...
  2. A

    Wreal study material

    Can somebody provide link to documents of WREAL modelling . I am trying to convert all the electrical models to wreal models.
  3. A

    N-bit ADC vams model

    Re: N bit Adc vams model analog begin V(VREF)<+ 0.7 + (TRIM * 0.0266667); max_1=V(VREF) + 0.6; min_1=V(VREF) - 0.6; // min_1=0; fullscale_1=max_1+min_1; midpoint1=fullscale_1/2.0; end always@( posedge (CLK_IN) or !(fault_avdd) ) begin //if (!(fault_avdd)) // begin sample1=V(VIN)...
  4. A

    N-bit ADC vams model

    N bit Adc vams model I am modelling a 12 bit ADC in vams. The input range is 0.3 to 1.5V. i.e 0.3 = 000'H and 1.2V = FFF'H. Need your help in selecting midpoint values max= 1.5; min=0.3 fullscale = max-min; midpoint = fullscale/2.0; This logic doesnt work.
  5. A

    IF LOOP in Verilog A not working for 0.7

    `include "constants.vams" `include "disciplines.vams" module TG(VDD,GND,GAIN,OFFSET,TRIM,THRESHOLD); input GAIN,VDD,GND,OFFSET,THRESHOLD; output [15:0] TRIM; electrical GAIN,VDD,GND,OFFSET,THRESHOLD; electrical[15:0] TRIM; electrical gnd; ground gnd; real gain_1; real offset_1; real total...
  6. A

    IF LOOP in Verilog A not working for 0.7

    `include "constants.vams" `include "disciplines.vams" module TG(VDD,GND,GAIN,OFFSET,TRIM,THRESHOLD); input GAIN,VDD,GND,OFFSET,THRESHOLD; output [15:0] TRIM; electrical GAIN,VDD,GND,OFFSET,THRESHOLD; electrical[15:0] TRIM; electrical gnd; ground gnd; real gain_1; real offset_1; real total...
  7. A

    IF LOOP in Verilog A not working for 0.7

    I have 5 to 6 if loops comparing different values like 0.6V,0.5V,0.4V. So cannot go with the above solution. I also tried with V(THRESHOLD1,GND)>0.699999 && V(THRESHOLD1,GND)<0.7000001 and its working.. Even in case statement I am not able to verify with 0.7 whereas other values are working
  8. A

    IF LOOP in Verilog A not working for 0.7

    Hi All, I am unable to enter this if loop, if (V(THRESHOLD1,GND)==0.7) begin V(TRIM[14])<+V(VDD); V(TRIM[13])<+V(GND);V(TRIM[12])<+V(VDD);V(TRIM[11])<+V(VDD);V(TRIM[10])<+V(VDD);V(TRIM[9])<+V(VDD); dummy1=V(VDD); dummy2=V(GND);dummy3=V(VDD);dummy4=V(VDD);dummy5=V(VDD);dummy6=V(VDD); end...
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