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Recent content by arifboy

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    Multiple varying delays to signals in VHDL

    Dont waste my time anymore, my focus is towards my code and algorithms which can be implemented on it, not towards people like you
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    Multiple varying delays to signals in VHDL

    Its the same, I just added those lines of you with signal checker..Intiially there is extra cycle added as you see in waveform. It is taking an extra cycle instead of just one, to make Alu_logic a 1. You cant simulate it at your end? 1742951406 You yourself dont know VHDL, thats why you...
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    Multiple varying delays to signals in VHDL

    With your suggestion the waveform came closer to what the expected waveform is, but still not exactly there. I have attached a photo of that. You suggested if, I used while too with other lines exactly as you mentioned, but that didn't work too according to expectation.
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    Multiple varying delays to signals in VHDL

    This is program code, not the testbench. I was using after previously as you mentioned but second after nullifies first one for each of if else above. Wait actually is doing something at least, but output is not right one. I think its not possible to simulate it in this way in VHDL, at least by...
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    Multiple varying delays to signals in VHDL

    In Simulations, the waveforms which I target must be possible, but I failed to get using both 'wait' and 'after' and even with combo of these two too. So maybe I am missing some key points. Synthesis can be achieved by a different approach, but first thing is Simulations and get the required...
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    Multiple varying delays to signals in VHDL

    I am working on a VHDL code to insert multiple varying delays to signals. I have shown code below and expected waveforms and present waveforms respectively too. How can the code be changed to get desired waveforms? Code: int := conv_integer(pc); wait until rising_edge(clk)...
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