arifboy's latest activity

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arifboy replied to the thread Multiple varying delays to signals in VHDL.

Dont waste my time anymore, my focus is towards my code and algorithms which can be implemented on it, not towards people like you

Yesterday at 8:54 AM
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arifboy replied to the thread Multiple varying delays to signals in VHDL.

Its the same, I just added those lines of you with signal checker..Intiially there is extra cycle added as you see in waveform. It is...

Yesterday at 12:57 AM
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arifboy replied to the thread Multiple varying delays to signals in VHDL.

With your suggestion the waveform came closer to what the expected waveform is, but still not exactly there. I have attached a photo of...
Tuesday at 4:16 PM
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arifboy replied to the thread Multiple varying delays to signals in VHDL.

This is program code, not the testbench. I was using after previously as you mentioned but second after nullifies first one for each of...

Monday at 1:32 PM
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arifboy replied to the thread Multiple varying delays to signals in VHDL.

In Simulations, the waveforms which I target must be possible, but I failed to get using both 'wait' and 'after' and even with combo of...

Saturday at 11:45 AM
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arifboy posted the thread Multiple varying delays to signals in VHDL in PLD, SPLD, GAL, CPLD, FPGA Design.

I am working on a VHDL code to insert multiple varying delays to signals. I have shown code below and expected waveforms and present...
Saturday at 3:58 AM