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I am doing my final year project of 4 bit processor design. There, I need to construct a 4 bit divider. I am doing this project by schematic diagram. I want a logic diagram for this. Can anyone help me? I have got a diagram from internet, but I think it is wrong, as there are 0-6 dividends, but...
I want to make a 8051 MCU based digital clock which will be shown on lcd 16x2. (JHD 162A). I want the assembly language program for that. I want the particular code that will circulate a loop in a particular LCD address. What will be the program? Please help me.
I have compiled in keil uvision 4.Programmer is Willar programmer. Anyway, I have sorted it out. now another WARNING is occuring when I am trying to compile in keil uvision 4.
Code:
ORG 000BH
START: MOV P0,#0C0H
LCALL DLY
MOV P0,#0F9H
LCALL DLY
DLY: MOV R6,#30H
HERE: DJNZ R6,HERE
RET
END...
Hi,
I have written a program on 7 segment display interfacing. It will count from 0-9. These is a warning every time, I can't get where is the error. Moreover, I am burning the program into my AT89C51 IC, but it is not working as per program.
1. First, please have a look at my code and errors...
what i have ran , i have uploaded the code and it is simulated properly and i have got the waveform, now my question is that-- Is the waveform right what i have got???
her is my code, by using this code, i have got the waveform.. is the waveform right??
entity dff is
Port ( D: in std_logic;
CLK : in std_logic;
Q : out std_logic;
QN : out std_logic);
end dff;
architecture Behavioral of dff is
begin
process...
please post the vhdl program for d flip-flop. and also the test bench waveform(only the waveform, not its programming).
i have uploaded the test bench waveform of d flip flop, how to check if it is right?
there is no Add option, it says that it allows only .vhd, .ngc, .ngo file s are allowed. what will i do now? anyone can please tell me the steps i have to used to successfully simulate this program? i am using xilinx ise 9.2i design suite. the xilinx directory is in E:\ drive
hi !! i was designing a full adder using two half adder using the following program, but constantly i got the same error. please help me. any suggestion is acceptable.
the name of vhd file is fulladd.vhd.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use...
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