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Thanks for the suggestions.
A small update: I showed the measurement setup to an expert designer. He was pretty confident that the chip malfunction, along with the high power consumption, is due to oscillations of internal nodes. The reasons could be related to wrong layout choices such as a...
dick_freebird, thank you for your detailed reply. That is actually the only help I got.
The layout is DRC-clean. This was also confirmed by our silicon provider. Is it possible for a fabricated chip without DRC problems to exhibit latchup issues?
Please keep in mind that, as I specified in...
Hi dick_freebird and thanks for your reply.
Please could you explain what do you mean by "limit the travel"?
Digital outputs seem to assume a fixed random voltage (e.g., 100 mV, 1 V, etc) and they do not oscillate. That's really strange since they are outputs of basic CMOS inverters (custom...
Dear all,
I designed a mixed signal asic with tsmc 65 nm process for research purposes. A lab expert suggested me to avoid the pad ring for speeding up the gds delivery. Now I'm trying to measure the fabricated chip and I'm experiencing a very strange behavior from the circuit. In short, it...
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