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I have programmable FIR filters in my design that are consuming DSP resources what should be done in this aspect keeping in view I cant reduce data type and filter order
I am trying to implement an AM demodulator on ZYNQ 706 FPGA. To ensure the quality of output I need a higher Fixed Data type. this required a large number of DSP slices. Is there any method to reduce the number of DSP slices without reducing the DATA TYPE
can you please elaborate in detail I am using Simulink for this purpose
I have tried it using the downsampling block in Simulink
No, I need that low-intensity signal
I have multiple data channels in the 20MHz band while a single channel bandwidth is not more than 12k
I am trying to downsample a 20MHz signal to a 1MHz signal. while doing this signal the low-intensity signal is skipped. Another issue arising due to Downsampling is Aliasing. I have to demodulate the downsampled signal. On demodulating the single channel, there is audio from another channel what...
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