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Recent content by aditya1579

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    clock skew degradation

    Hi, I am seeing my clock skew degrade between cts and cts_optimization What could be possible reasons ? What can be done to resolve this ? Regards.
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    Phase Shift in timing calculation / reports

    Hi, In my timing runs, I see that the phase shift appears as 0.5ns in the timing reports. But since the rest of the reports is in ps, I see a huge slack (WNS). How do I resolve this to make the tool take 500ps as the phase shift, thus correcting the slack no to where it should be ? The clock...
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    Error in Calibre

    Hi , what is the meaning of the following error : ERROR: Another cell record encountered for cell ....... This is coming while trying to run calibredrv Thanks, Aditya
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    Erc viols meaning

    Hi, What is the meaning of mnpg violation in Erc check ? Thanks Aditya
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    blitz++ files in laker

    Hi, How are blitz++ files generated in Synopsys laker ? What are they used for ? Thanks.
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    Command in Innovus to balance 1 clock

    Hi, One clock in my design is not balanced, which command should I use in Innovus to balance just this one clock? All other clocks look fine, Aditya
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    How to split a power domain

    Hi, In my design, all memories belong to one power domain. But since they are spread all over the block, how do I split the power domain to place it wherever the memories are present ? Thanks, Aditya
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    Question on power domains

    Hi, I have 2 power domains in my design. The memories operate at one voltage and the std cell logic at another. I was asked to place only one voltage domain, the std cell logic one. The sram one is not placed as such. BUt still I see proper power gnd connections to the pins of the memories...
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    Power Domains

    Hi, My question is - if the power domain is mentioned in the UPF, then why does a separate entity of type power domain (it can be queried by pressing Q or query) show up in the design, especially in Innovus ? is it necessary to place this ? Thanks, Aditya
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    Meaning of voltage in middle of library name

    Hi, In some library names, there is a voltage in the middle of the lib name, independent of the characterization voltage. What does this voltage signify ? For eg : TSMC 40nm LP 1.1 V LVT process. Here what is 1.1 V ? This is not characterization voltage.
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    DDR interface explanation

    HI I have not fully understood how a DDR interface works. If the data bits read a byte of data at the rising edge of the clock, how come the same bits see new data at the falling egde of the clock, because the data bits would be pointing to the same location in the memory for the full clock...
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    DRC rules for Double Pattern Test

    Hi All, Can anyone list out a few DRC rules specially formulated for double patterning in lower tech nodes like 7nm etc ? Thanks, Aditya
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    Floorplanning Guidelines for TSMC 7nm

    Can you please elaborate on why keeping poly unidirectional and aligned will help in pushing the process technology further ?
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    Floorplanning Guidelines for TSMC 7nm

    Thank you very much for your reply. Can you please elaborate on why keeping poly unidirectional and aligned will help in pushing the process technology further ? What is the meaning of gridded ?
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    Floorplanning Guidelines for TSMC 7nm

    Hi All, Can any one please let me know why in TSMC 7nm, all poly's are supposed to be in a straight line ? Also what do different colored tracks and macro pins signify ? I have noticed that in my project there were yellow and red colored macro pins which had to sit below similar colored...
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