PLD, SPLD, GAL, CPLD, FPGA Design

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Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.
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My VHDL Code is giving unexpected value after simulating with Floating point IP cores
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Soh_bhat
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Floating point IP cores Latency problem
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dpaul
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Difference between LPDDR4 single-rank and dual-rank with ECC interface
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engr_joni_ee
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How to extract input/reg size in Verilog?
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7
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ads-ee
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Connect Microblaze to AXI4-Lite
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dpaul
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USART Interrupt in Zynq
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dolrairom
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[SOLVED] Access BRAM from PS
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aminpix
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[SOLVED] Multiplier on VHDL explanation
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kaz1
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[SOLVED] Vhdl feedback implementation
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Vhdlontherise
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Sine quantization using ROM
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danadakk
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[SOLVED] VHDL code bug in sim - please help me
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FvM
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Read multimedia from MicroSD and display on HDMI
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dpaul
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Best way to find the nth root of a number using VHDL.
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KlausST
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Metastability
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danadakk
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is it hard microsd driver?
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FlyingDutch
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Xilinx FPGA with Erased QR Code
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3
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pbernardi
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FPGA PR error message
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5
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Fun-King
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Declaration of a constant that chooses among other constants of different sizes in vhdl
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10
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rafimiet
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gating reset signal
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YuanJin
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[SOLVED] object cannot be indexed because it has natural type rather than array type
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Akanimo
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