PLD, SPLD, GAL, CPLD, FPGA Design

Post thread
Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.
  • Locked
Can anyone checking my work about FSM/VHDL
Replies
5
Views
2K
ads-ee
P
  • Locked
usbcorev verilog softcore questions
Replies
0
Views
1K
promach
P
C
  • Locked
How to add the ip core of a FIFO using tcl console in ISE 14.5?
Replies
5
Views
1K
dpaul
C
  • Locked
[SOLVED] How to read the data from a fifo memory after a certain time?
Replies
9
Views
2K
Cesar0182
C
S
  • Locked
CPLD for project
Replies
3
Views
2K
danadakk
S
  • Locked
How to make bus skew in a reasonable range with FPGA port
Replies
10
Views
3K
ads-ee
  • Locked
[SOLVED] Dealing with RAM in VHDL
Replies
17
Views
6K
saifaljanahi
C
  • Locked
How can I put together two codes in Quartus
Replies
4
Views
2K
Akanimo
A
T
  • Locked
Verilog with multiple if conditions
Replies
4
Views
2K
fenglei
V
  • Locked
NIOS II Address Width Issue
Replies
0
Views
955
velu.plg
V
A
  • Locked
Aurora 8b/10b data incorrect issue.
Replies
4
Views
2K
avinashc
A
S
  • Locked
Solution of GRC (Global Routing Congestion)
Replies
4
Views
2K
seunghok
S
M
  • Locked
[SOLVED] Why some modules don't appear in the Netlist after synthesis using Vivado 2019.1
Replies
6
Views
4K
MSAKARIM
M
E
  • Locked
Converting table files (.tbl) to vector waveform files (.vwf) for simulation.
Replies
0
Views
678
echotwozero
E
  • Locked
Some problem with DPLL
Replies
0
Views
557
fenglei
M
  • Locked
double-edged clock in VHDL
Replies
7
Views
3K
kaz1
K
D
  • Locked
How to calculate throughput in Xilinx vivado?
Replies
4
Views
3K
kaz1
K
  • Locked
Alternative for VHDL 2008 "alias"
Replies
3
Views
2K
TrickyDicky
T
M
  • Locked
Partial reconfiguration
Replies
1
Views
845
ads-ee
B
  • Locked
Looking for a free project kit emulator
Replies
9
Views
2K
TrickyDicky
T
Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…