PLD, SPLD, GAL, CPLD, FPGA Design

Post thread
Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.
J
  • Locked
Question about phase locking
Replies
1
Views
2K
Big Boy
B
Q
  • Locked
Sysgen error: netlist is empty. cannot trim useless hardware
Replies
0
Views
2K
QuIcK-SiLvEr
Q
J
  • Locked
Is it possible to implement a modem using FPGAs?
Replies
6
Views
4K
mc_navman
M
V
  • Locked
Vhd & ImageProcess ?! help!!!
Replies
1
Views
1K
ahmadagha23
A
L
  • Locked
A Placement-aware Retiming And Replication Method for FPGA
Replies
0
Views
2K
ljkong
L
L
  • Locked
FPGAs: Fast Track to DSP（one paper from mentor&am
Replies
0
Views
1K
ljkong
L
H
  • Locked
Does anyone have been used the DC-FPGA(Syn0psys)?
Replies
4
Views
2K
eda_wiz
E
X
  • Locked
Advice about development board
Replies
1
Views
2K
meemee2
M
J
  • Locked
Power calculation of FPGA..
Replies
1
Views
2K
maestor
M
S
  • Locked
webcast on back end ic design
Replies
0
Views
1K
supra924
S
  • Locked
How to program SPI Flash devices via JTAG?
Replies
2
Views
6K
Mazi3
M
H
  • Locked
I need schematic to implement a program on FPGA board
Replies
3
Views
2K
cube007
C
M
  • Locked
These verilog codes are robust enough?
Replies
0
Views
2K
malfunction
M
M
  • Locked
Is 50 Celsius a normal temperature of a CPLD ?
Replies
4
Views
2K
malfunction
M
T
  • Locked
whether Voice-crosstalk need to be considered ?
Replies
1
Views
1K
mc_navman
M
E
  • Locked
Forward error checking for FPGA data transfer
Replies
1
Views
2K
mc_navman
M
B
  • Locked
Programming Altera FPGA via USB
Replies
2
Views
4K
blue_phoenix
B
R
  • Locked
How to use VERILOG PLI and when is it needed?
Replies
3
Views
2K
jimjim2k
J
P
  • Locked
Need documentations about bus interfacing
Replies
0
Views
1K
picus
P
  • Locked
How to patch Protel 2004 to add Spartan support?
Replies
2
Views
2K
SPATAN
S
Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…