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Mastering Design Rule Checking (DRC) for High-Quality IC Design

Screen Shot 2024-09-08 at 22.36.22.png
Screen Shot 2024-09-08 at 22.36.22.png

For signoff engineers in the integrated circuit (IC) industry, mastering Design Rule Checking (DRC) in physical verification is crucial for ensuring high-quality and reliable designs. This blog explores advanced DRC methodologies, specific case studies, and the latest cutting-edge technologies in digital design.

Importance of DRC in Ensuring IC Quality​

Design Rule Checking (DRC) is a vital step in the IC design flow, ensuring that the physical layout adheres to manufacturing process constraints. Effective DRC helps identify potential issues early, reducing costly iterations and enhancing overall product quality.

Essential Techniques in DRC​

1. Hierarchical DRC
Hierarchical DRC involves verifying design rules at different levels of the design hierarchy, allowing for efficient and scalable verification of complex SoCs.

Case Study:
A team at Nvidia implemented hierarchical DRC using customized scripts integrated with Verdi. This approach allowed them to check logic functions, clocking, timing, power, and DFT at both RTL and gate levels. The integration with Verdi provided a GUI that linked error reports directly to the design context, significantly improving debug efficiency.

Implementation:
Block-Level Verification:
Conduct DRC at the block level to simplify top-level verification.
Tool Integration:Use tools like Verdi for seamless integration of hierarchical DRC with design context.

2. Automated DRC Fixes
Automated DRC tools like BindKey's Rapid Design Clean (RDC) and Rapid Design Fix (RDF) offer on-the-fly DRC error detection and correction, enhancing productivity.

Case Study:
BindKey's RDC and RDF tools were used in conjunction with Cadence Virtuoso to perform online DRC checks and automatic fixes. These tools provided graphical hints, enforced rules, and notified users of errors, significantly reducing verification time and improving yield.

Implementation:
Online DRC Checks:
Implement tools that offer real-time DRC checks during design.
Automated Fixes:Use tools like RDC and RDF for automatic error correction.

Advanced Techniques in DRC​

1. Physically Aware DRC
Physically aware DRC incorporates physical design constraints into the verification process, ensuring accurate detection and correction of errors related to placement and routing.

Case Study:
A semiconductor company used Synopsys Hercules for physically aware DRC, integrating the tool with their Milkyway database. This integration allowed for direct read/write access, improving the efficiency of DRC processes and ensuring accurate error detection.

Implementation:
Physical Constraints Integration:
Use DRC tools that integrate physical design constraints.
Database Integration:Leverage databases like Milkyway for direct interaction with DRC tools.

2. Power-Aware DRC
Power-aware DRC involves checking for design rule violations that could affect power integrity, essential for low-power and high-performance designs.

Case Study:
Mentor Graphics' Calibre was used to perform power-aware DRC checks, ensuring that designs met stringent power requirements without sacrificing performance. The tool's robust algorithms provided accurate and fast verification, helping designers maintain power integrity across complex designs.

Implementation:
Power Integrity Checks:
Implement DRC tools that focus on power-related rule checks.
Low-Power Techniques:Use techniques like multi-threshold voltage cells and clock gating to ensure compliance with power rules.
About author
Peng Yu
With a wealth of experience in formal verification projects, I specialize in two critical solutions: formal signoff with full proof and formal signoff with coverage. Throughout my career, I have successfully tackled a diverse range of designs, including Instruction units, Standard interfaces, User-defined interfaces, Bus matrices, Caches, MMUs, Schedulers, DMA controllers, Memory controllers, Interrupt controllers, Power management units, and various specific functional modules.

Drawing on this extensive project experience and a deep understanding of various design types, I have developed a unique formal verification methodology. This methodology has been honed through practical application and has proven highly effective in ensuring design correctness and efficiency.

One of my key achievements has been the independent creation of a comprehensive formal verification IP library. This library comprises nearly 200 units, encompassing basic, common, VIP, and flow libraries. These resources, combined with my methodology, have been successfully deployed in the product development workflows of numerous leading chip companies. The results speak for themselves, with significant improvements in verification effectiveness and performance observed across the board.

My goal is to share this expertise with students at EDA Academy, providing them with practical insights and industry best practices that they can apply directly to their own projects. By imparting this knowledge, I aim to empower learners to achieve their verification goals with confidence and efficiency.

EDA Academy:https://www.eda-academy.com
Explore our current Formal Verification courses:
  1. Introduction to Formal Verification
  2. Formal Verification: SVA Coding
  3. Formal Verification: PSL Coding

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Peng Yu
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