Formal Methods for High-Quality Protocol Verification


Formal verification has become an essential component in the verification process of complex protocols. By employing formal verification tool, the process of verifying High-Quality Protocol has been significantly enhanced. This blog explores the advanced formal verification techniques and the technical challenges encountered during the verification of the High-Quality Protocol.

Formal Verification Environment​

The formal verification environment is meticulously designed to handle the complexities of the High-Quality Protocol. This environment facilitates the parallel proving of properties, ensuring that all critical properties are verified simultaneously. Each property is categorized as either under computation, proven, or found to have counterexamples. This categorization helps in prioritizing and managing the verification process effectively.

Figure 1. formal verification environment

Tackling the Top Challenge: Bound Proof​

One of the significant challenges in formal verification is the bound proof. This involves proving properties up to a certain bound, beyond which the proof becomes impractically complex. To address this, the formal verification team employed various strategies, such as:
  • Assumptions Management: Properly managing assumptions to avoid conflicts and ensuring they align with the design.
  • Engine Selection: Choosing the appropriate verification engines to maximize efficiency and coverage.
  • Complexity Reduction: Breaking down complex assertions into smaller, manageable properties to reach deeper proofs.
Coding Style and Data Integrity
A disciplined coding style is crucial for effective formal verification. For instance, in the High-Quality Protocol verification, specific coding practices were followed to ensure data integrity:
  • Stable Properties: Ensuring that properties remain stable across clock cycles.
  • Boundary Conditions: Verifying boundary conditions to prevent errors during edge cases.
  • Assertions: Utilizing assertions to verify the integrity of data paths and control signals.

Error Cases and Formal Checks​

Formal verification excels in identifying various error cases that traditional simulation might miss. For example, the High-Quality Protocol verification identified errors such as data loss, duplication, and switching. These error cases were meticulously covered through formal checks, ensuring that the design handled all possible scenarios robustly.

Proof Accelerator and Initial Value Abstraction​

The proof accelerator in formal verification tool significantly enhances the verification process by speeding up the proof of complex properties. Formal verification tool, combined with initial value abstraction, helps in verifying properties from an initial state to their eventual state, ensuring thorough coverage. The relationship between the link layer and the protocol layer is verified using these advanced techniques, providing a comprehensive verification solution.

Managing Over-Constraints​

Over-constraining the design can lead to false positives or missed bugs. The verification process involves carefully managing constraints to ensure that they do not overly restrict the design space. By balancing constraints, the verification team can explore a broader range of scenarios, leading to a more robust verification process.

Figure 2. managing over-constraints

Bound Proof and Bug Hunting​

Bound proof is a compromise between verification effort and quality. The verification team employed techniques to push the boundaries as deeplyas possible, ensuring critical features are thoroughly verified. Additionally, extensive bug hunting within the bounded proof case revealed several environmental and RTL problems, which were then addressed in subsequent design iterations.

Figure 3. bound proof and bug hunting
About author
With a wealth of experience in formal verification projects, I specialize in two critical solutions: formal signoff with full proof and formal signoff with coverage. Throughout my career, I have successfully tackled a diverse range of designs, including Instruction units, Standard interfaces, User-defined interfaces, Bus matrices, Caches, MMUs, Schedulers, DMA controllers, Memory controllers, Interrupt controllers, Power management units, and various specific functional modules.

Drawing on this extensive project experience and a deep understanding of various design types, I have developed a unique formal verification methodology. This methodology has been honed through practical application and has proven highly effective in ensuring design correctness and efficiency.

One of my key achievements has been the independent creation of a comprehensive formal verification IP library. This library comprises nearly 200 units, encompassing basic, common, VIP, and flow libraries. These resources, combined with my methodology, have been successfully deployed in the product development workflows of numerous leading chip companies. The results speak for themselves, with significant improvements in verification effectiveness and performance observed across the board.

My goal is to share this expertise with students at EDA Academy, providing them with practical insights and industry best practices that they can apply directly to their own projects. By imparting this knowledge, I aim to empower learners to achieve their verification goals with confidence and efficiency.

EDA Academy:https://www.eda-academy.com
Explore our current Formal Verification courses:
  1. Introduction to Formal Verification
  2. Formal Verification: SVA Coding
  3. Formal Verification: PSL Coding

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