Continue to Site

Blog list

talius
Updated
Entries
5
With increasing use of IP building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages/netlist formats (VHDL, system verilog, verilog, SPEF/DSPF, SPICE etc). For an all-in-one analysis and...

Part and Inventory Search

Back
Top