Static Timing Analysis

Project : pulse test
Build Time : 08/12/22 13:36:23
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
SPIM_IntClock CyMASTER_CLK 8.000 MHz 8.000 MHz 63.207 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 125ns(8 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:RxStsReg\/status_6 63.207 MHz 15.821 109.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \SPIM:BSPIM:rx_status_4\ \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:rx_status_6\/main_5 6.086
macrocell4 U(3,4) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_5 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.305
statusicell2 U(3,4) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 69.190 MHz 14.453 110.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 3.676
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 73.562 MHz 13.594 111.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.817
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 73.681 MHz 13.572 111.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.795
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 73.681 MHz 13.572 111.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.795
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 74.566 MHz 13.411 111.589
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.634
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 77.779 MHz 12.857 112.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 3.676
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.391
statusicell1 U(2,4) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:RxStsReg\/status_6 81.387 MHz 12.287 112.713
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:rx_status_6\/main_4 4.192
macrocell4 U(3,4) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_4 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.305
statusicell2 U(3,4) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:TxStsReg\/status_3 83.347 MHz 11.998 113.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.817
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.391
statusicell1 U(2,4) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:TxStsReg\/status_3 83.500 MHz 11.976 113.024
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.795
macrocell1 U(3,5) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.391
statusicell1 U(2,4) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_2\/main_3 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_2\/main_3 2.619
macrocell8 U(3,5) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_1\/main_3 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_1\/main_3 2.619
macrocell9 U(3,5) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:ld_ident\/main_3 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:ld_ident\/main_3 2.619
macrocell12 U(3,5) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 Net_317/main_5 3.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 Net_317/main_5 2.634
macrocell7 U(3,5) 1 Net_317 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 2.783
macrocell8 U(3,5) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_1\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_1\/main_5 2.783
macrocell9 U(3,5) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:ld_ident\/main_5 3.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:ld_ident\/main_5 2.783
macrocell12 U(3,5) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 2.793
macrocell8 U(3,5) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 2.793
macrocell9 U(3,5) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:ld_ident\/main_6 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:ld_ident\/main_6 2.793
macrocell12 U(3,5) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_IntClock
Source Destination Delay (ns)
xp_miso_data(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 17.293
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 xp_miso_data(0)_PAD xp_miso_data(0)_PAD xp_miso_data(0)/pad_in 0.000
iocell17 P0[4] 1 xp_miso_data(0) xp_miso_data(0)/pad_in xp_miso_data(0)/fb 7.563
Route 1 Net_320 xp_miso_data(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 6.230
datapathcell1 U(3,5) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPIM_IntClock
Source Destination Delay (ns)
Net_317/q xp_data(0)_PAD 23.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,5) 1 Net_317 Net_317/clock_0 Net_317/q 1.250
Route 1 Net_317 Net_317/q xp_data(0)/pin_input 6.942
iocell13 P0[0] 1 xp_data(0) xp_data(0)/pin_input xp_data(0)/pad_out 15.251
Route 1 xp_data(0)_PAD xp_data(0)/pad_out xp_data(0)_PAD 0.000
Clock Clock path delay 0.000
Net_231/q xp_serial_clock(0)_PAD 23.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 Net_231 Net_231/clock_0 Net_231/q 1.250
Route 1 Net_231 Net_231/q xp_serial_clock(0)/pin_input 6.651
iocell12 P0[2] 1 xp_serial_clock(0) xp_serial_clock(0)/pin_input xp_serial_clock(0)/pad_out 15.459
Route 1 xp_serial_clock(0)_PAD xp_serial_clock(0)/pad_out xp_serial_clock(0)_PAD 0.000
Clock Clock path delay 0.000
Net_239/q xp_ss(0)_PAD 22.809
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,4) 1 Net_239 Net_239/clock_0 Net_239/q 1.250
Route 1 Net_239 Net_239/q xp_ss(0)/pin_input 5.815
iocell14 P0[3] 1 xp_ss(0) xp_ss(0)/pin_input xp_ss(0)/pad_out 15.744
Route 1 xp_ss(0)_PAD xp_ss(0)/pad_out xp_ss(0)_PAD 0.000
Clock Clock path delay 0.000