Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.3 (WebPack) - P.40xd Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 21ebd0d61038488bb74489e8754fa1b4.F4D169E9FD8A4D0796F73663FA566B6D.24 Target Package: fg320
Registration ID 204973097_0_0_679 Target Speed: -4
Date Generated 2013-04-22T21:58:11 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=3
  • 13-bit subtractor=2
  • 21-bit adder=1
Comparators=7
  • 11-bit comparator greatequal=2
  • 11-bit comparator less=4
  • 21-bit comparator less=1
Counters=8
  • 11-bit up counter=4
  • 17-bit up counter=1
  • 27-bit up counter=1
  • 32-bit up counter=2
Latches=1
  • 1-bit latch=1
Multipliers=2
  • 13x13-bit multiplier=2
Registers=249
  • Flip-Flops=249
MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_SLICE=1273
  • NUM_4_INPUT_LUT=1585
  • NUM_BONDED_IBUF=2
  • NUM_BONDED_IOB=10
  • NUM_BUFGMUX=3
  • NUM_CYMUX=573
  • NUM_IOB_LATCH=8
  • NUM_LUT_RT=138
  • NUM_MULT18X18SIO=6
  • NUM_MULTAND=1
  • NUM_SHIFT=61
  • NUM_SLICEL=1218
  • NUM_SLICEM=55
  • NUM_SLICE_FF=1609
  • NUM_XOR=438
  • Xilinx Core floating_point_v5_0, Xilinx CORE Generator 14.3=4
NetStatistics
  • NumNets_Active=2522
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMDUMMY=302
  • NumNodesOfType_Active_CLKPIN=1049
  • NumNodesOfType_Active_CNTRLPIN=261
  • NumNodesOfType_Active_DOUBLE=3991
  • NumNodesOfType_Active_DUMMY=4186
  • NumNodesOfType_Active_DUMMYBANK=85
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=191
  • NumNodesOfType_Active_HFULLHEX=47
  • NumNodesOfType_Active_HLONG=2
  • NumNodesOfType_Active_HUNIHEX=162
  • NumNodesOfType_Active_INPUT=5559
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=2420
  • NumNodesOfType_Active_OUTPUT=2388
  • NumNodesOfType_Active_PREBXBY=1982
  • NumNodesOfType_Active_VFULLHEX=126
  • NumNodesOfType_Active_VLONG=13
  • NumNodesOfType_Active_VUNIHEX=206
  • NumNodesOfType_Gnd_BRAMDUMMY=72
  • NumNodesOfType_Gnd_CLKPIN=2
  • NumNodesOfType_Gnd_DOUBLE=30
  • NumNodesOfType_Gnd_DUMMY=188
  • NumNodesOfType_Gnd_DUMMYBANK=11
  • NumNodesOfType_Gnd_INPUT=298
  • NumNodesOfType_Gnd_OMUX=115
  • NumNodesOfType_Gnd_OUTPUT=65
  • NumNodesOfType_Gnd_PREBXBY=37
  • NumNodesOfType_Gnd_VFULLHEX=7
  • NumNodesOfType_Vcc_BRAMDUMMY=16
  • NumNodesOfType_Vcc_CNTRLPIN=50
  • NumNodesOfType_Vcc_DUMMY=56
  • NumNodesOfType_Vcc_INPUT=116
  • NumNodesOfType_Vcc_PREBXBY=44
  • NumNodesOfType_Vcc_VCCOUT=90
SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=4
  • IOB-DIFFS=4
  • SLICEL-SLICEM=513
SiteSummary
  • BUFGMUX=3
  • BUFGMUX_GCLKMUX=3
  • BUFGMUX_GCLK_BUFFER=3
  • IBUF=2
  • IBUF_INBUF=2
  • IBUF_PAD=2
  • IOB=10
  • IOB_OFF1=8
  • IOB_OUTBUF=10
  • IOB_PAD=10
  • MULT18X18SIO=6
  • MULT18X18SIO_MULT18X18SIO=6
  • SLICEL=1218
  • SLICEL_C1VDD=8
  • SLICEL_C2VDD=6
  • SLICEL_CYMUXF=287
  • SLICEL_CYMUXG=270
  • SLICEL_F=759
  • SLICEL_F5MUX=43
  • SLICEL_F6MUX=2
  • SLICEL_FAND=1
  • SLICEL_FFX=795
  • SLICEL_FFY=739
  • SLICEL_G=744
  • SLICEL_GNDF=184
  • SLICEL_GNDG=174
  • SLICEL_VDDG=1
  • SLICEL_XORF=225
  • SLICEL_XORG=203
  • SLICEM=55
  • SLICEM_C1VDD=1
  • SLICEM_CYMUXF=8
  • SLICEM_CYMUXG=8
  • SLICEM_F=27
  • SLICEM_FFX=24
  • SLICEM_FFY=51
  • SLICEM_G=55
  • SLICEM_GNDF=7
  • SLICEM_GNDG=8
  • SLICEM_WSGEN=47
  • SLICEM_XORF=6
  • SLICEM_XORG=4
 
Configuration Data
BUFGMUX
  • S=[S_INV:3] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:3]
  • S=[S_INV:3] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:2]
IOB
  • O1=[O1_INV:0] [O1:10]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:8]
  • SR=[SR:8] [SR_INV:0]
IOB_OFF1
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • LATCH_OR_FF=[LATCH:8]
  • OFF1_INIT_ATTR=[INIT1:8]
  • OFF1_SR_ATTR=[SRHIGH:8]
  • OFFATTRBOX=[ASYNC:8]
  • SR=[SR:8] [SR_INV:0]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:10]
IOB_PAD
  • DRIVEATTRBOX=[12:10]
  • IOATTRBOX=[LVCMOS25:10]
  • SLEW=[SLOW:10]
MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:6]
  • CEB=[CEB_INV:0] [CEB:6]
  • CEP=[CEP:6] [CEP_INV:0]
  • CLK=[CLK:6] [CLK_INV:0]
  • RSTA=[RSTA:6] [RSTA_INV:0]
  • RSTB=[RSTB:6] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:6]
MULT18X18SIO_MULT18X18SIO
  • AREG=[0:6]
  • BREG=[0:6]
  • B_INPUT=[DIRECT:6]
  • CEA=[CEA_INV:0] [CEA:6]
  • CEB=[CEB_INV:0] [CEB:6]
  • CEP=[CEP:6] [CEP_INV:0]
  • CLK=[CLK:6] [CLK_INV:0]
  • PREG=[0:2] [1:4]
  • PREG_CLKINVERSION=[0:6]
  • RSTA=[RSTA:6] [RSTA_INV:0]
  • RSTB=[RSTB:6] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:6]
SLICEL
  • BX=[BX_INV:4] [BX:363]
  • BY=[BY:435] [BY_INV:4]
  • CE=[CE:131] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:269]
  • CLK=[CLK:986] [CLK_INV:0]
  • SR=[SR:122] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:287] [0_INV:0]
  • 1=[1_INV:0] [1:287]
SLICEL_CYMUXG
  • 0=[0:269] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:43] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:2] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:120] [CE_INV:0]
  • CK=[CK:795] [CK_INV:0]
  • D=[D:791] [D_INV:4]
  • FFX_INIT_ATTR=[INIT0:793] [INIT1:2]
  • FFX_SR_ATTR=[SRLOW:789] [SRHIGH:6]
  • LATCH_OR_FF=[FF:795]
  • REV=[REV_INV:0] [REV:12]
  • SR=[SR:98] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:689] [SYNC:106]
SLICEL_FFY
  • CE=[CE:130] [CE_INV:0]
  • CK=[CK:739] [CK_INV:0]
  • D=[D:735] [D_INV:4]
  • FFY_INIT_ATTR=[INIT0:725] [INIT1:14]
  • FFY_SR_ATTR=[SRLOW:723] [SRHIGH:16]
  • LATCH_OR_FF=[FF:739]
  • REV=[REV_INV:0] [REV:10]
  • SR=[SR:111] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:615] [SYNC:124]
SLICEL_XORF
  • 1=[1_INV:0] [1:225]
SLICEM
  • BX=[BX_INV:0] [BX:17]
  • BY=[BY:47] [BY_INV:0]
  • CIN=[CIN_INV:0] [CIN:8]
  • CLK=[CLK:51] [CLK_INV:0]
  • SR=[SR:47] [SR_INV:0]
SLICEM_CYMUXF
  • 0=[0:8] [0_INV:0]
  • 1=[1_INV:0] [1:8]
SLICEM_CYMUXG
  • 0=[0:8] [0_INV:0]
SLICEM_F
  • DI=[DI:14] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:14]
  • LUT_OR_MEM=[LUT:13] [RAM:14]
SLICEM_FFX
  • CK=[CK:24] [CK_INV:0]
  • D=[D:24] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:24]
  • FFX_SR_ATTR=[SRLOW:24]
  • LATCH_OR_FF=[FF:24]
  • SYNC_ATTR=[ASYNC:24]
SLICEM_FFY
  • CK=[CK:51] [CK_INV:0]
  • D=[D:51] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:51]
  • FFY_SR_ATTR=[SRLOW:51]
  • LATCH_OR_FF=[FF:51]
  • SYNC_ATTR=[ASYNC:51]
SLICEM_G
  • DI=[DI:47] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:47]
  • LUT_OR_MEM=[LUT:8] [RAM:47]
SLICEM_WSGEN
  • CK=[CK:47] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:47]
  • WE=[WE_INV:0] [WE:47]
SLICEM_XORF
  • 1=[1_INV:0] [1:6]
 
Pin Data
BUFGMUX
  • I0=3
  • O=3
  • S=3
BUFGMUX_GCLKMUX
  • I0=3
  • OUT=3
  • S=3
BUFGMUX_GCLK_BUFFER
  • IN=3
  • OUT=3
IBUF
  • I=2
  • PAD=2
IBUF_INBUF
  • IN=2
  • OUT=2
IBUF_PAD
  • PAD=2
IOB
  • O1=10
  • OTCLK1=8
  • PAD=10
  • SR=8
IOB_OFF1
  • CK=8
  • D=8
  • Q=8
  • SR=8
IOB_OUTBUF
  • IN=10
  • OUT=10
IOB_PAD
  • PAD=10
MULT18X18SIO
  • A0=6
  • A1=6
  • A10=6
  • A11=6
  • A12=6
  • A13=6
  • A14=6
  • A15=6
  • A16=6
  • A17=6
  • A2=6
  • A3=6
  • A4=6
  • A5=6
  • A6=6
  • A7=6
  • A8=6
  • A9=6
  • B0=6
  • B1=6
  • B10=6
  • B11=6
  • B12=6
  • B13=6
  • B14=6
  • B15=6
  • B16=6
  • B17=6
  • B2=6
  • B3=6
  • B4=6
  • B5=6
  • B6=6
  • B7=6
  • B8=6
  • B9=6
  • CEA=6
  • CEB=6
  • CEP=6
  • CLK=6
  • P0=6
  • P1=6
  • P10=6
  • P11=6
  • P12=6
  • P13=6
  • P14=5
  • P15=5
  • P16=5
  • P17=5
  • P18=5
  • P19=5
  • P2=6
  • P20=5
  • P21=3
  • P22=3
  • P23=3
  • P24=1
  • P25=1
  • P26=1
  • P27=1
  • P28=1
  • P29=1
  • P3=6
  • P30=1
  • P31=1
  • P32=1
  • P33=1
  • P4=6
  • P5=6
  • P6=6
  • P7=6
  • P8=6
  • P9=6
  • RSTA=6
  • RSTB=6
  • RSTP=6
MULT18X18SIO_MULT18X18SIO
  • A0=6
  • A1=6
  • A10=6
  • A11=6
  • A12=6
  • A13=6
  • A14=6
  • A15=6
  • A16=6
  • A17=6
  • A2=6
  • A3=6
  • A4=6
  • A5=6
  • A6=6
  • A7=6
  • A8=6
  • A9=6
  • B0=6
  • B1=6
  • B10=6
  • B11=6
  • B12=6
  • B13=6
  • B14=6
  • B15=6
  • B16=6
  • B17=6
  • B2=6
  • B3=6
  • B4=6
  • B5=6
  • B6=6
  • B7=6
  • B8=6
  • B9=6
  • CEA=6
  • CEB=6
  • CEP=6
  • CLK=6
  • P0=6
  • P1=6
  • P10=6
  • P11=6
  • P12=6
  • P13=6
  • P14=5
  • P15=5
  • P16=5
  • P17=5
  • P18=5
  • P19=5
  • P2=6
  • P20=5
  • P21=3
  • P22=3
  • P23=3
  • P24=1
  • P25=1
  • P26=1
  • P27=1
  • P28=1
  • P29=1
  • P3=6
  • P30=1
  • P31=1
  • P32=1
  • P33=1
  • P4=6
  • P5=6
  • P6=6
  • P7=6
  • P8=6
  • P9=6
  • RSTA=6
  • RSTB=6
  • RSTP=6
SLICEL
  • BX=367
  • BY=439
  • CE=131
  • CIN=269
  • CLK=986
  • COUT=270
  • F1=732
  • F2=657
  • F3=485
  • F4=193
  • F5=4
  • FXINA=2
  • FXINB=2
  • G1=735
  • G2=660
  • G3=498
  • G4=166
  • SR=122
  • X=147
  • XB=18
  • XQ=795
  • Y=307
  • YQ=739
SLICEL_C1VDD
  • 1=8
SLICEL_C2VDD
  • 1=6
SLICEL_CYMUXF
  • 0=287
  • 1=287
  • OUT=287
  • S0=287
SLICEL_CYMUXG
  • 0=269
  • 1=270
  • OUT=270
  • S0=270
SLICEL_F
  • A1=731
  • A2=657
  • A3=485
  • A4=193
  • D=759
SLICEL_F5MUX
  • F=39
  • G=43
  • OUT=43
  • S0=43
SLICEL_F6MUX
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
SLICEL_FAND
  • 0=1
  • 1=1
  • O=1
SLICEL_FFX
  • CE=120
  • CK=795
  • D=795
  • Q=795
  • REV=12
  • SR=98
SLICEL_FFY
  • CE=130
  • CK=739
  • D=739
  • Q=739
  • REV=10
  • SR=111
SLICEL_G
  • A1=735
  • A2=660
  • A3=498
  • A4=166
  • D=744
SLICEL_GNDF
  • 0=184
SLICEL_GNDG
  • 0=174
SLICEL_VDDG
  • 1=1
SLICEL_XORF
  • 0=225
  • 1=225
  • O=225
SLICEL_XORG
  • 0=203
  • 1=203
  • O=203
SLICEM
  • BX=17
  • BY=47
  • CIN=8
  • CLK=51
  • COUT=8
  • F1=25
  • F2=25
  • F3=20
  • F4=15
  • G1=55
  • G2=55
  • G3=51
  • G4=47
  • SR=47
  • XB=4
  • XQ=24
  • YQ=51
SLICEM_C1VDD
  • 1=1
SLICEM_CYMUXF
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEM_CYMUXG
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEM_F
  • A1=25
  • A2=25
  • A3=20
  • A4=15
  • D=27
  • DI=14
  • WS=14
SLICEM_FFX
  • CK=24
  • D=24
  • Q=24
SLICEM_FFY
  • CK=51
  • D=51
  • Q=51
SLICEM_G
  • A1=55
  • A2=55
  • A3=51
  • A4=47
  • D=55
  • DI=47
  • WS=47
SLICEM_GNDF
  • 0=7
SLICEM_GNDG
  • 0=8
SLICEM_WSGEN
  • CK=47
  • WE=47
  • WSF=14
  • WSG=47
SLICEM_XORF
  • 0=6
  • 1=6
  • O=6
SLICEM_XORG
  • 0=4
  • 1=4
  • O=4
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 595 595 0 0 0 0 0
edif2ngd 5 5 0 0 0 0 0
map 596 591 0 0 0 0 0
netgen 43 43 0 0 0 0 0
ngc2edif 25 25 0 0 0 0 0
ngcbuild 175 175 0 0 0 0 0
ngdbuild 605 605 0 0 0 0 0
obngc 42 42 0 0 0 0 0
par 584 584 0 0 0 0 0
trce 570 570 0 0 0 0 0
xst 1101 1074 0 0 0 0 0
 
Help Statistics
Search words with results
Register Port ( 1 )
Unsuccessful Search words
Register Port A Output of memory Core ( 1 )
Help files
/doc/usenglish/isehelp/cgn_c_cust_gui_overview.htm ( 1 ) /doc/usenglish/isehelp/cgn_c_define_mem_contents.htm ( 1 )
/doc/usenglish/isehelp/cgn_c_define_values_coe_file.htm ( 1 ) /doc/usenglish/isehelp/cgn_r_coe_file_syntax.htm ( 1 )
/doc/usenglish/isehelp/cgn_r_naming_gen_cores.htm ( 1 ) /doc/usenglish/isehelp/pim_cl_batch_command_definitions_s.htm ( 1 )
/doc/usenglish/isehelp/pim_r_boundaryscan_basics.htm ( 1 ) /doc/usenglish/isehelp/sse_db_obsolete_symbols.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/Test_positioner
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=Schematic PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-02-03T17:47:00
PROP_intWbtProjectID=F4D169E9FD8A4D0796F73663FA566B6D PROP_intWbtProjectIteration=24
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.Test_positioner
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=false
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_COREGEN=4
FILE_SCHEMATIC=1 FILE_UCF=1
FILE_VERILOG=6
 
Core Statistics
Core Type=floating_point_v5_0
c_a_fraction_width=0 c_a_width=32 c_b_fraction_width=0 c_b_width=32
c_compare_operation=8 c_has_a_nd=0 c_has_a_negate=0 c_has_a_rfd=0
c_has_aclr=0 c_has_add=0 c_has_b_nd=0 c_has_b_negate=0
c_has_b_rfd=0 c_has_ce=0 c_has_compare=0 c_has_cts=0
c_has_divide=0 c_has_divide_by_zero=0 c_has_exception=0 c_has_fix_to_flt=1
c_has_flt_to_fix=0 c_has_flt_to_flt=0 c_has_inexact=0 c_has_invalid_op=0
c_has_multiply=0 c_has_operation_nd=0 c_has_operation_rfd=0 c_has_overflow=0
c_has_rdy=0 c_has_sclr=0 c_has_sqrt=0 c_has_status=0
c_has_subtract=0 c_has_underflow=0 c_latency=6 c_mult_usage=0
c_optimization=1 c_rate=1 c_result_fraction_width=24 c_result_width=32
c_speed=2 c_status_early=0 c_xdevicefamily=spartan3e
Core Type=floating_point_v5_0
c_a_fraction_width=24 c_a_width=32 c_b_fraction_width=24 c_b_width=32
c_compare_operation=8 c_has_a_nd=0 c_has_a_negate=0 c_has_a_rfd=0
c_has_aclr=0 c_has_add=0 c_has_b_nd=0 c_has_b_negate=0
c_has_b_rfd=0 c_has_ce=0 c_has_compare=0 c_has_cts=0
c_has_divide=0 c_has_divide_by_zero=0 c_has_exception=0 c_has_fix_to_flt=0
c_has_flt_to_fix=1 c_has_flt_to_flt=0 c_has_inexact=0 c_has_invalid_op=0
c_has_multiply=0 c_has_operation_nd=0 c_has_operation_rfd=0 c_has_overflow=0
c_has_rdy=0 c_has_sclr=0 c_has_sqrt=0 c_has_status=0
c_has_subtract=0 c_has_underflow=0 c_latency=6 c_mult_usage=0
c_optimization=1 c_rate=1 c_result_fraction_width=0 c_result_width=32
c_speed=2 c_status_early=0 c_xdevicefamily=spartan3e
Core Type=floating_point_v5_0
c_a_fraction_width=24 c_a_width=32 c_b_fraction_width=24 c_b_width=32
c_compare_operation=8 c_has_a_nd=0 c_has_a_negate=0 c_has_a_rfd=0
c_has_aclr=0 c_has_add=0 c_has_b_nd=0 c_has_b_negate=0
c_has_b_rfd=0 c_has_ce=0 c_has_compare=0 c_has_cts=0
c_has_divide=0 c_has_divide_by_zero=0 c_has_exception=0 c_has_fix_to_flt=0
c_has_flt_to_fix=0 c_has_flt_to_flt=0 c_has_inexact=0 c_has_invalid_op=0
c_has_multiply=1 c_has_operation_nd=0 c_has_operation_rfd=0 c_has_overflow=0
c_has_rdy=0 c_has_sclr=0 c_has_sqrt=0 c_has_status=0
c_has_subtract=0 c_has_underflow=0 c_latency=6 c_mult_usage=2
c_optimization=1 c_rate=1 c_result_fraction_width=24 c_result_width=32
c_speed=2 c_status_early=0 c_xdevicefamily=spartan3e
Core Type=floating_point_v5_0
c_a_fraction_width=24 c_a_width=32 c_b_fraction_width=24 c_b_width=32
c_compare_operation=8 c_has_a_nd=0 c_has_a_negate=0 c_has_a_rfd=0
c_has_aclr=0 c_has_add=0 c_has_b_nd=0 c_has_b_negate=0
c_has_b_rfd=0 c_has_ce=0 c_has_compare=0 c_has_cts=0
c_has_divide=0 c_has_divide_by_zero=0 c_has_exception=0 c_has_fix_to_flt=0
c_has_flt_to_fix=0 c_has_flt_to_flt=0 c_has_inexact=0 c_has_invalid_op=0
c_has_multiply=0 c_has_operation_nd=0 c_has_operation_rfd=0 c_has_overflow=0
c_has_rdy=0 c_has_sclr=0 c_has_sqrt=0 c_has_status=0
c_has_subtract=1 c_has_underflow=0 c_latency=13 c_mult_usage=0
c_optimization=1 c_rate=1 c_result_fraction_width=24 c_result_width=32
c_speed=2 c_status_early=0 c_xdevicefamily=spartan3e
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=347 NGDBUILD_NUM_FDC=11
NGDBUILD_NUM_FDCE=11 NGDBUILD_NUM_FDE=1057 NGDBUILD_NUM_FDR=107 NGDBUILD_NUM_FDRS=121
NGDBUILD_NUM_FDS=9 NGDBUILD_NUM_FDSE=14 NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_INV=21 NGDBUILD_NUM_LDP_1=8 NGDBUILD_NUM_LUT1=105 NGDBUILD_NUM_LUT2=370
NGDBUILD_NUM_LUT2_D=2 NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=458 NGDBUILD_NUM_LUT3_D=97
NGDBUILD_NUM_LUT3_L=79 NGDBUILD_NUM_LUT4=304 NGDBUILD_NUM_LUT4_D=6 NGDBUILD_NUM_LUT4_L=50
NGDBUILD_NUM_MULT18X18SIO=6 NGDBUILD_NUM_MULT_AND=1 NGDBUILD_NUM_MUXCY=592 NGDBUILD_NUM_MUXF5=43
NGDBUILD_NUM_MUXF6=4 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_SRL16=52
NGDBUILD_NUM_SRLC16E=9 NGDBUILD_NUM_VCC=5 NGDBUILD_NUM_XORCY=446
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_FD=347 NGDBUILD_NUM_FDC=11 NGDBUILD_NUM_FDCE=11
NGDBUILD_NUM_FDE=1057 NGDBUILD_NUM_FDR=107 NGDBUILD_NUM_FDRS=121 NGDBUILD_NUM_FDS=9
NGDBUILD_NUM_FDSE=14 NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=21 NGDBUILD_NUM_LDP_1=8 NGDBUILD_NUM_LUT1=105 NGDBUILD_NUM_LUT2=370
NGDBUILD_NUM_LUT2_D=2 NGDBUILD_NUM_LUT2_L=3 NGDBUILD_NUM_LUT3=458 NGDBUILD_NUM_LUT3_D=97
NGDBUILD_NUM_LUT3_L=79 NGDBUILD_NUM_LUT4=304 NGDBUILD_NUM_LUT4_D=6 NGDBUILD_NUM_LUT4_L=50
NGDBUILD_NUM_MULT18X18SIO=6 NGDBUILD_NUM_MULT_AND=1 NGDBUILD_NUM_MUXCY=592 NGDBUILD_NUM_MUXF5=43
NGDBUILD_NUM_MUXF6=4 NGDBUILD_NUM_MUXF7=2 NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_SRLC16E=61
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=5 NGDBUILD_NUM_XORCY=446
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-verilog2001=YES -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -mult_style=Auto -iobuf=YES -max_fanout=100000
-bufg=24 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=unisims_ver
Fuse Resource Usage=1140 ms, 40056 KB