vgademo2 Project Status (04/22/2013 - 21:58:17)
Project File: Project4.xise Parser Errors: No Errors
Module Name: vgademo2 Implementation State: Synthesized
Target Device: xc3s500e-4fg320
  • Errors:
 
Product Version:ISE 14.3
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 1156 4656 24%
Number of Slice Flip Flops 1713 9312 18%
Number of 4 input LUTs 1497 9312 16%
Number of bonded IOBs 12 232 5%
Number of MULT18X18SIOs 4 20 20%
Number of GCLKs 2 24 8%
 
Detailed Reports [+]
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentMon Apr 22 21:31:34 2013
WebTalk ReportCurrentMon Apr 22 21:58:11 2013
WebTalk Log FileCurrentMon Apr 22 21:58:17 2013

Date Generated: 04/22/2013 - 21:58:17