vgademo2 Project Status (04/22/2013 - 21:58:17) | |||
Project File: | Project4.xise | Parser Errors: | No Errors |
Module Name: | vgademo2 | Implementation State: | Synthesized |
Target Device: | xc3s500e-4fg320 |
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Product Version: | ISE 14.3 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 1156 | 4656 | 24% | |
Number of Slice Flip Flops | 1713 | 9312 | 18% | |
Number of 4 input LUTs | 1497 | 9312 | 16% | |
Number of bonded IOBs | 12 | 232 | 5% | |
Number of MULT18X18SIOs | 4 | 20 | 20% | |
Number of GCLKs | 2 | 24 | 8% |
Detailed Reports | [+] |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Mon Apr 22 21:31:34 2013 | |
WebTalk Report | Current | Mon Apr 22 21:58:11 2013 | |
WebTalk Log File | Current | Mon Apr 22 21:58:17 2013 |