Core name: Xilinx LogiCORE Floating Point Operator
                Version: 5.0
                Release: ISE 14.1
                Release Date: April 24 2012


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This document contains the following sections:

1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Other Information
8. Core Release History
9. Legal Disclaimer

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1. INTRODUCTION

For installation instructions for this release, please go to:

   www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Floating Point Operator v5.0
solution. For the latest core updates, see the product page at:

   www.xilinx.com/products/ipcenter/FLOATING_PT.htm


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2. NEW FEATURES

  - ISE 14.1 software support
  - ISE 13.4 software support
  - ISE 13.3 software support
  - ISE 13.2 software support
  - Support for Artix-7 with ISE 13.2
  - ISE 13.1 software support, Virtex-7 and Kintex-7 support
  - ISE 12.1 software support
  - Support for Virtex-6Q and Spartan-6Q with ISE 12.1
  - ISE 11.4 software support
  - Support for Automotive Spartan-6 with ISE 11.4
  - Support for Spartan-6 Low Power with ISE 11.4
  - Support for Virtex-6 Low Power and Virtex-5Q with ISE 11.3
  - Support for Virtex-6, Spartan-6, with ISE 11.2


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3. SUPPORTED DEVICES
 
The following device families are supported by the core for this release.

  All 7 Series devices

  All Virtex-6 devices

  All Spartan-6 devices

  All Virtex-5 devices

  All Virtex-4 devices

  All Spartan-3 devices


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4. RESOLVED ISSUES

   - Support for -u map option for all operators (for use with PlanAhead)
     - CR470172
     - All operators should now go through map with -u option specified.

   - SCLR/CE priority clarification in datasheet
     - CR470376
     - The behavior that SCLR overrides CE is now also mentioned in the
       description of the SCLR port in Table 2.

   - Datasheet should clearly state that SCLR does not clear datapath
     - CR487995
     - The behavior that SCLR only resets control path is now explicitly
       mentioned in the description of the SCLR port in Table 2.

   - Datasheet documents HDL generics - this interface is no longer supported
     - CR470377
     - The only supported customer interface for core generation is through
       CORE Generator GUI. The description of the HDL generics has been
       removed from the datasheet.

   - Datasheet should be enhanced with numerical examples
     - CR477962
     - An example C-code program has been provided in the datasheet to
       enable customers to replicate core behavior at single precision with a
       desktop computer. This assumes that denormalized numbers are not used.
       This code can be used to generate hexadecimal values for comparison
       with an HDL simulation of the core.

   - SCLR should be greyed out in GUI when not applicable
     - CR483358
     - SCLR and CE are no longer available when latency is set to zero, as
       there is no clock port.

   - Datasheet has incorrect equation (page 2, bounds for fractional part)
     - CR481413
     - The lower bound for the fractional part (with hidden bit) is now correctly
       specified as 1. That is: 1 <= b0.b1...bp-1 < 2.


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5. KNOWN ISSUES

The following are known issues for v5.0 of this core at time of release:

  - None

The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at

   www.xilinx.com/support/documentation/user_guides/xtp025.pdf


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6. TECHNICAL SUPPORT

To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.


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7. OTHER INFORMATION

  - None


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8. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
04/24/2012  Xilinx, Inc.  5.0          ISE 14.1 support
01/11/2012  Xilinx, Inc.  5.0          ISE 13.4 support
10/19/2011  Xilinx, Inc.  5.0          ISE 13.3 support
06/22/2011  Xilinx, Inc.  5.0          ISE 13.2 support, Artix-7 support
03/01/2011  Xilinx, Inc.  5.0          ISE 13.1 support, Virtex-7 and Kintex-7 support
10/29/2010  Xilinx, Inc.  5.0          ISE 7 Series Monthly Snapshot - (O.28)
04/19/2010  Xilinx, Inc.  5.0          ISE 12.1, Virtex-6Q and Spartan-6Q support
12/02/2008  Xilinx, Inc.  5.0          11.2 support, Spartan-6L support and Automotive Spartan6 support
09/16/2008  Xilinx, Inc.  5.0          11.3 support, Virtex-6L support
06/24/2008  Xilinx, Inc.  5.0          11.2 support, Virtex-6, Spartan-6 support
04/25/2008  Xilinx, Inc.  4.0          10.1i support
09/28/2006  Xilinx, Inc.  3.0          8.2i support
01/18/2006  Xilinx, Inc.  2.0          8.1i support
04/28/2005  Xilinx, Inc.  1.0          Initial release
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9. LEGAL DISCLAIMER

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