Xilinx Processor IP Library

Change log for proc_common





 

Changes in 3.00a introduced in 13.2

13.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Added zynq to family_support.vhd
  • Updated coregen_comp_defs.vhd, async_fifo_fg.vhd, and sync_fifo_fg.vhd
    • Updated the used fifo_generator version to v8.2 for virtex6/spartan6 and later root device famlies
  • blk_mem_gen_wrapper.vhd
    • Updated the used version of blk_mem_gen to v6.2 for virtex6/spartan6 and later root device famlies
  • Added a new file named  basic_sfifo_fg.vhd that supports a simple single clock FIFO with First Word Fall Through (FWFT)
    • Uses FIFO Generator 8.2 under the hood

Resolved Issues: Develpment CRs CR595473, CR595477, CR595478, CR596052, CR596280, CR602290, CR604652

 

Known Issues / Limitations:

  •  CR565755 (Spyglass Lint issue.. not a functional issue)

 





 

Changes in 3.00a introduced in 13.1

13.1 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Added virtex7 and kintex7 to family_support.vhd
  • Updated coregen_comp_defs.vhd, async_fifo_fg.vhd, and sync_fifo_fg.vhd
    • Updated the fifo_generator version to v8.1 for virtex6, spartan6, virtex7, and kintex7 root device famlies
  • blk_mem_gen_wrapper.vhd
    • Retained the blk_mem_gen version to v5.2 for virtex6, spartan6, virtex7, and kintex7 root device famlies
    • blk_mem_gen version v6.1 is not backwards compatable with v5.2

Resolved Issues:

 

Known Issues / Limitations:

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Changes in 3.00a introduced in 12.4

12.4 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Added a new function in family_support.vhd to derive the root device family and supported part status
  • Updated coregen_comp_defs.vhd, async_fifo_fg.vhd, and sync_fifo_fg.vhd
    • Updated the fifo_generator version to v7.2 for v6 and S6 root device famlies
  • Updated blk_mem_gen_wrapper.vhd
    • Updated the blk_mem_gen version to v4.3 for v6 and S6 root device famlies

Resolved Issues:
  • Per CR573867: Improved derivative part aliasing to root fpga family
    • Updated async_fifo_fg.vhd and sync_fifo_fg.vhd
      • Modified to use the new root family function in family_support.vhd
      • Added checking logic for unsupported part families
    • Updated blk_mem_gen_wrapper.vhd
      • Modified to use the new root family function in family_support.vhd
      • Added checking logic for unsupported part families

 

Known Issues / Limitations:

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Changes in 3.00a introduced in 12.2

12.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Added Virtex6 and Spartan6 derivative part support as well as qrvirtex5
    • Added qrvirtex5 to family_support.vhd
    • Updated async_fifo_fg.vhd and sync_fifo_fg.vhd to support spartan6l, qspartan6, aspartan6.virtex6l, qspartan6l, qrvirtex5, and qvirtex6.
    • Updated blk_mem_gen_wrapper.vhd to support spartan6l, qspartan6, aspartan6.virtex6l, qspartan6l, qrvirtex5, and qvirtex6.
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Resolved Issues:

 

Known Issues / Limitations:

  •  

 

 

Changes in 3.00a introduced in 12.1

12.1 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Migrated to the new Xilinx FIFO Generator and Block Memory Generator Technology
    • Updated the coregen_comp_defs.vhd file to add out the latest Xilinx Fifo Generator components (fifo_generator_v6_1) and the latest Xilinx Block MemGen component (blk_mem_gen_v4_1) .
    • Updated async_fifo_fg.vhd and sync_fifo_fg.vhd to call fifo_generator_6_1 instead of fifo_generator_5_3 for S6 and V6 FPGA families.
    • Updated blk_mem_gen_wrapper.vhd to call out blk_mem_gen_4_1 instead of blk_mem_gen_3_3 for S6 and V6 FPGA families.
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Resolved Issues:

 

Known Issues / Limitations:

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Changes in 3.00a introduced in 11.3

11.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • None
     

Resolved Issues:
  • Corrected a redundant entry of the mux_onehot_f file name in the PAO file.  This change is per CR528607.

 

Known Issues / Limitations:

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Changes in 3.00a introduced in 11.2

11.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Migrated to the new Xilinx FIFO Generator and Block Memory Generator Technology
    • Updated the coregen_comp_defs.vhd file to add out the latest Xilinx Fifo Generator components (fifo_generator_v5_1 and fifo_generator_v5_2) and the latest Xilinx Block MemGen component (blk_mem_gen_v3_2) in place of the old CoreGen components declared in the previous version of the coregen_comp_defs.vhd file.
    • Updated async_fifo_fg.vhd and sync_fifo_fg.vhd to call fifo_generator_5_2 instead of fifo_generator_5_1
    • Updated blk_mem_gen_wrapper.vhd to call out blk_mem_gen_3_2 instead of blk_mem_gen_3_1
       

Resolved Issues:
  • Corrected a tool build issue with blk_mem_gen_3_1
  • Changed the log2 function in proc_common_pkg.vhd so that it will no longer generate XST Warnings regarding the assertion statement.  This change is per CR520627.

 

Known Issues / Limitations:

  •  

 

Changes in 3.00a introduced in 11.1

11.1 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


New Features:
  • Migrated to the new Xilinx FIFO Generator and Block Memory Generator Technology
    • Revamped the coregen_comp_defs.vhd file to call out the latest Xilinx Fifo Generator components (fifo_generator_v4_2 and fifo_generator_v4_3) and the latest Xilinx Block MemGen component (blk_mem_gen_v2_7) in place of the old CoreGen components declared in the previous version of the coregen_comp_defs.vhd file.
      • Removed support for: cam_v5_0, async_fifo_v4_0, async_fifo_v5_1, async_fifo_v6_0, async_fifo_v6_1, sync_fifo_v4_0, sync_fifo_v5_0
    • Added new file blk_mem_gen_wrapper.vhd wrapper file to be used in conjunction with the new coregen_comp_defs.vhd file and the new Block Memory Generator utility for implementing BRAM based memory functions called from HDL.
    • Added new file async_fifo_fg.vhd wrapper file to be used in conjunction with the new coregen_comp_defs.vhd file and the new fifo generator utility for implementing async fifos compatible with the old CoreGen async fifo implementations called from HDL.
    • Added new file sync_fifo_fg.vhd wrapper file to be used in conjunction with the new fifo generator utility for implementing sync fifos compatible with the old CoreGen sync fifo implementations called from HDL.
       
  • Updated/Changed FPGA Family support in the file family_support.vhd
    • Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp, qvirtex4, qrvirtex4
    • Removed family: aspartan3an
    • The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead of BSCAN_SPARTAN3E

Resolved Issues:
  • Srl_fifo_rbu_f was changed in a minor, functionally equivalent way to allow the current XST to infer a better implementation of the FIFO_Full signal. CR<496211>

 

Known Issues / Limitations:

  •