Change log for axi_timer



Changes in v1.03.a, introduced in 13.3

13.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)



 New Features:
  • Cascade mode is introduced for supporting 64-bit timer operation [CR#611074]
Resolved Issues:
  • None
Known Issues /Limitations:
  • None

13.3 - Changes in documentation associated with core



  • Cascade mode added to support 64-bit timer operation (CR#611074)


Changes in v1.02.a, introduced in 13.2


13.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)
New Features:
  • None
Resolved Issues:
  • Interrupt is made a level signal and widths of few signals reduced to avoid warnings during ngdbuild
Known Issues / Limitations:
  • None

Changes in v1.01.a, introduced in 12.4


12.4 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)
New Features:
  • None
Resolved Issues:
  • axi lite ipif v1.01.a used to reduce the resource utilization
Known Issues / Limitations:
  • None


Changes in v1.00.a, introduced in 12.3


12.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)

New Features:

  • First version of the axi_timer_v1_00_a IP
Resolved Issues:
  • None
Known Issues / Limitations:
  • None