Xilinx Processor IP Library

Change log for AXI Interconnect


Changes in v1.06.a, introduced in 14.5

Note: Unless specified, limitations and resolved issues affect all previous versions.

14.5 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)

Known Issues / Limitations:
  • Setting parameter C_S_AXI_IS_INTERCONNECT = 1 is not supported.

  • The diagnostic control interface (S_AXI_CTRL) is not implemented. The parameter C_USE_CTRL_PORT is therefore forced to 0.


14.5 - Changes in tool interface files (.mpd)


14.5 - Changes in tool interface files (.pao)


14.5 - Changes in Tcl script files associated with core (.tcl)

Resolved issues:
  • Core-generated XDC updated per recommended XDC standards (applies only to Vivado-XPS flow).


14.5 - Changes in IP Configuration GUI (.ui)


14.5 - Changes in documentation associated with core


Changes in v1.06.a, introduced in 14.4

Note: Unless specified, limitations and resolved issues affect all previous versions.

14.4 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)

Known Issues / Limitations:
  • Setting parameter C_S_AXI_IS_INTERCONNECT = 1 is not supported.

  • The diagnostic control interface (S_AXI_CTRL) is not implemented. The parameter C_USE_CTRL_PORT is therefore forced to 0.


14.4 - Changes in tool interface files (.mpd)


14.4 - Changes in tool interface files (.pao)


14.4 - Changes in Tcl script files associated with core (.tcl)

Resolved issues:
  • When using the Vivado implementation flow, the axi_interconnect core generates XDC timing constraints for each asynchronous clock-domain crossing. Beginning in 14.4, these timing constraints are based on clock periods defined in your system-level XDC (using create_clock). If a system-level clock definition is missing for the AXI ACLK pin on either side of any async conversion, implementation will issue critical warnings.


14.4 - Changes in IP Configuration GUI (.ui)


14.4 - Changes in documentation associated with core


Changes in v1.06.a, introduced in 14.1

Note: Unless specified, limitations and resolved issues affect all previous versions.

14.1 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)

New Features:
  • Synchronous clock-domain crossings are performed completely within the clock converter module, so multi-cycle clock constraints are no longer necessary and are no longer generated. ACLK period parameter is used only for async clock conversions, and the async CDC clock constraints will still succeed using a TIG, even if the ACLK period is not specified.

  • Asynchronous clock-domain crossings are now performed using a single instance of 5-channel AXI FIFO (per interface slot) instead of 5 separate calls to fifo_generator, thereby decreasing compilation time. Timing constraints for async CDC are now conditionally generated only if the interconnect instance performs any async conversions.

  • Initial release of v1.06.


14.1 - Changes in tool interface files (.mpd)


14.1 - Changes in tool interface files (.pao)


14.1 - Changes in Tcl script files associated with core (.tcl)

New Features:
  • Added Optimization Alerts for conditions including C_INTERCONNECT_DATA_WIDTH narrower than widest MI or different than all SI/MI slots, C_INTERCONNECT_ACLK_RATIO slower than fastest MI or different than all SI/MI slots, redundant 32-deep FIFO with async clock-conv, Type-1 reg-slice on AW/AR/B channel or AXI4-Lite slot, SAMD crossbar with all AXI4-Lite masters/slaves.


14.1 - Changes in IP Configuration GUI (.ui)


14.1 - Changes in documentation associated with core


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