Changes in v4.03.a, introduced in 13.3 |
13.3 - Changes in VHDL/Verilog/Netlist sources (.vhd,
.v, .ngc, .edn) |
|
13.3 - Changes in tool interface files (.mpd) |
|
13.3 - Changes in documentation associated with
core |
|
Changes in v4.02.a, introduced in 13.2 |
13.2 - Changes in VHDL/Verilog/Netlist sources (.vhd,
.v, .ngc, .edn) |
|
13.2 - Changes in tool interface files (.mpd) |
|
13.2 - Changes in documentation associated with
core |
|
Changes in v4.01.a, introduced in 12.4.0 |
12.4.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn) |
|
12.4.0 - Changes in tool interface files (.mpd) |
|
12.4.0 - Changes in documentation associated with core |
|
Changes in v4.00.a, introduced in 12.1.0 |
12.1.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn) |
|
12.1.0 - Changes in tool interface files (.mpd) |
|
12.1.0 - Changes in documentation associated with core |
|
|
Changes in v3.02.a, introduced in 11.4.0 |
11.4.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn) |
None |
11.4.0 - Changes in tool interface files (.mpd) |
When user Virtex-6
design does not enable variable phase on the feedback clock, namely the value
of parameter C_PSDONE_GROUP is not MMCM<i>_FB, there is no difference
between the 2 versions. When you enable the
variable phase on the feedback clock of a Virtex-6 design, namely the value
of parameter C_PSDONE_GROUP is MMCM<i>_FB the values of parameter
C_CLKOUT<i>_VARIABLE_PHASE have opposite implications between these 2
versions. For v3.01.a core,
when C_CLKOUT<i>_VARIABLE_PHASE is TRUE, the corresponding clock output
from the core has a fixed phase shift; when the value is FALSE, the phase of
the corresponding clock output from the core is dynamically shifted. For v3.02.a core,
when C_CLKOUT<i>_VARIABLE_PHASE is FLASE, the corresponding clock
output from the core has fixed phase shift; when the value is TRUE, the phase
of the corresponding clock output from the core is dynamically shifted. The following
tables summarize the differences.
|
11.4.0 - Changes in documentation associated with core |
|
|
Changes in v3.01.a, introduced in 11.2.0 |
11.2.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn) |
New Features:
Resolved Issues:
Known Issues / Limitations:
|
11.2.0 - Changes in tool interface files (.mpd) |
|
11.2.0 - Changes in documentation associated with core |
|
|
Changes in v3.00.a, introduced in 11.1.0 |
11.1.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn) |
New Features:
Resolved Issues:
Known Issues / Limitations:
|
11.1.0 - Changes in tool interface files (.mpd) |
|
11.1.0 - Changes in Tcl script files associated with core (.tcl) |
|
11.1.0 - Changes in documentation associated with core |
|
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