Xilinx Processor IP Library

Change log for clock_generator


 

Changes in v4.03.a, introduced in 13.3

13.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  • None

13.3 - Changes in tool interface files (.mpd)


  • No new parameter has been added to v4.03. The data type of C_CLKOUTi_PHASE and C_CLKFBOUT_PHASE parameters have been changed from integer to real.

13.3 - Changes in documentation associated with core


  • Changed data type 

 

Changes in v4.02.a, introduced in 13.2

13.2 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  • Added plle2_module.vhd

13.2 - Changes in tool interface files (.mpd)


  • Clock Generator v4.02a introduced new high level parameters , C_CLKOUT0_DUTY_CYCLE to C_CLKOUT15_DUTY_CYCLE, have been added to v4.02a. The default value of these parameters is “0.5”. The user is not allowed to change these parameters from SAV by clicking on clock_generator v4.02a. The PLLE0 group has been added to the list of all C_CLKOUT*_GROUP.

13.2 - Changes in documentation associated with core


  • Added description to the newly introduced parameters. 

 

Changes in v4.01.a, introduced in 12.4.0

12.4.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  • None.

12.4.0 - Changes in tool interface files (.mpd)


  • Clock Generator v4.01a introduced a new high level parameters C_CLK_PRIMITIVE_FEEDBACK_BUF. It is valid only for Virtex6 family.

12.4.0 - Changes in documentation associated with core


  • Add description to the new introduced parameter. 

 

 

Changes in v4.00.a, introduced in 12.1.0

12.1.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  • Clock Generator v4.00a removes low level parameters used to be in previous versions. User is not able to directly manipulate the final clock circuitry and must rely on the core algorithm to generate the circuitry. The elaborated Clock Generator is described by the automatically generated clock_generaotor.vhd file.
  • The follwoing .vhd files that exist in v3.02a are removed in v4.00a:
    • clock_generator.vhd
    • mmcm_module_wrapper.vhd
    • pll_module_wrapper.vhd
    • dcm_module_wrapper.vhd
    • clock_selection.vhd
    • reset_selection.vhd

12.1.0 - Changes in tool interface files (.mpd)


  • Clock Generator v4.00a has same high level parameters as Clock Generator v3.02a.
  • To migrate the design with Clock Generator v3.02a to Clock Generator v4.00a, user can just change the core version from 3.02.a to 4.00.a and leave others unchanged. Please note the above does not work if low level parameters of Clock Generator v3.02a are used (PARAMETER C_CLK_GEN is defined in the design and its value is not “UPDATE”).

12.1.0 - Changes in documentation associated with core


  • Removed the table for Low Level Parameters for internal view. 

 

 


 

Changes in v3.02.a, introduced in 11.4.0

11.4.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  None

11.4.0 - Changes in tool interface files (.mpd)


 

  • The changes between versions 3.01.a and 3.02.a impact how user should use the core on Virtex-6 designs with variable phase enabled clocks.

When user Virtex-6 design does not enable variable phase on the feedback clock, namely the value of parameter C_PSDONE_GROUP is not MMCM<i>_FB, there is no difference between the 2 versions.

When you enable the variable phase on the feedback clock of a Virtex-6 design, namely the value of parameter C_PSDONE_GROUP is MMCM<i>_FB the values of parameter C_CLKOUT<i>_VARIABLE_PHASE have opposite implications between these 2 versions.

For v3.01.a core, when C_CLKOUT<i>_VARIABLE_PHASE is TRUE, the corresponding clock output from the core has a fixed phase shift; when the value is FALSE, the phase of the corresponding clock output from the core is dynamically shifted.

For v3.02.a core, when C_CLKOUT<i>_VARIABLE_PHASE is FLASE, the corresponding clock output from the core has fixed phase shift; when the value is TRUE, the phase of the corresponding clock output from the core is dynamically shifted.

The following tables summarize the differences.

    • For v3.01.a:
      • If C_PSDONE_GROUP = MMCMi (i=0~3) or NONE and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = TRUE, then CLKOUTi is variable phase shifted;
      • If C_PSDONE_GROUP = MMCMi (i=0~3) or NONE and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = FALSE, then CLKOUTi has fixed phase shift value;
      • If C_PSDONE_GROUP = MMCMi_FB (i=0~3) and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = TRUE, then CLKOUTi has fixed phase shift value;
      • If C_PSDONE_GROUP = MMCMi_FB (i=0~3) and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = FALSE, then CLKOUTi is variable phase shifted.
    • For v3.02.a:
      • If C_PSDONE_GROUP = MMCMi (i=0~3) or NONE and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = TRUE, then CLKOUTi is variable phase shifted;
      • If C_PSDONE_GROUP = MMCMi (i=0~3) or NONE and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = FALSE, then CLKOUTi has fixed phase shift value;
      • If C_PSDONE_GROUP = MMCMi_FB (i=0~3) and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = TRUE, then CLKOUTi is variable phase shifted;
      • If C_PSDONE_GROUP = MMCMi_FB (i=0~3) and C_CLKOUTi_VARIABLE_PHASE (i= 0~15) = FALSE, then CLKOUTi has fixed phase shift value
  • Clock_generator v3_01_a is deprecated on Virtex6 families; it is strongly suggested to use v3_02_a. Please follow the instruction, Changes between clock_generator v3.02.a and v3.01.a in the core datasheet to update the design using later version clock_generator.

11.4.0 - Changes in documentation associated with core


 

  • Add the "Parameter -  Meaniing Change" to describe the parameter value meaming change of  C_CLKOUTi_VARIABLE_PHASE (i= 0~15)

 

 


 

Changes in v3.01.a, introduced in 11.2.0

11.2.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  
New Features:
  • Virtex6 family devices can use up to 4 MMCM, variable phase shift is also supported
    • v3.01.a uses MMCM only, and does not uses DCM and PLL any more
  • Spartan6 family devices can use up to 2 PLL and 4 DCM, PLL to DCM cascading is also supported  
    • v3.01.a uses PLL as higher priority than uses DCM, while v3.00.a uses only DCM
Resolved Issues:
  • Virtex6 family devices use DCM and PLL, require DCM/PLL to MMCM retargeting tool to convert to MMCM 
    • Versions that have this issue: v3.00.a
  • Spartan6 family devices use DCM only
    • Versions that have this issue: v3.00.a

Known Issues / Limitations:

  • Variable phase shift is supported on Virtex6 family devices only
     

11.2.0 - Changes in tool interface files (.mpd)


 
  • Change the valid C_CLKOUTi_GROUP (i= 0~15) values for Virtex6 family devices
    • For v3.01.a: MMCMi (i= 0~3)
  • Change the valid C_CLKOUTi_GROUP (i= 0~15) values for Spartan6 family devices
    • For v3.01.a: DCMi (i=0~3) and PLLi (i= 0~1)
  • Add ports variable phase shift control: PSCLK, PSINCDEC, PSEN and PSDONE
  • Add parameters for variable phase shift: C_PSDONE_GROUP, C_CLKOUTi_VARIABLE_PHASE (i= 0~15)
  • Add MMCM parameters 

11.2.0 - Changes in documentation associated with core


 

  • Add figures to describe DCM/PLL/MMCM clock circut for different FPGA familiess
  • Add ports and parameters for variable phase shift control  
  • Add MMCM parameters 

 

 


 

Changes in v3.00.a, introduced in 11.1.0

11.1.0 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)


  
New Features:
  • Virtex5 family devices can use up to 2 PLL and 4 DCM, PLL to DCM cascading is also supported
  • Device specific clock circuit generation is supported
  • Improved error message and analyse in to log file
Resolved Issues:
  • Virtex5 family devices use only PLL except for external clock feedback 
    • Versions that have this issue: v2.01.a, v2.00.a

Known Issues / Limitations:


 

11.1.0 - Changes in tool interface files (.mpd)


 
  • The type of parameter C_CLK_GEN has been changed from integer to string, set to UPDATE to launch the clock circuit generation,  the value is changed to PASSED if clock circuit generation is successful, to FAILED otherwise

11.1.0 - Changes in Tcl script files associated with core (.tcl)


 
  • Change the way to capture return value of parameter C_CLK_GEN, exit with error when its value is not PASSED
     

11.1.0 - Changes in documentation associated with core


 

  • Replacing the line for parameter C_CLK_GEN, change the type of its value from integer to string
  • Remove the line for C_CLKIN_BUF and C_CLKFBIN_BUF