Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedSat Apr 13 09:36:50 2024 os_platformLIN64
product_versionVivado v2020.1 (64-bit) project_id557fc29781464754a719019d74ccaba4
project_iteration14 random_idfc6cfed8def65a8584ef038e5c02b6b1
registration_idfc6cfed8def65a8584ef038e5c02b6b1 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameAMD Ryzen 7 4800H with Radeon Graphics cpu_speed1735.063 MHz
os_nameUbuntu os_releaseUbuntu 23.10
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
abstractsearchablepanel_show_search=2 addsrcwizard_specify_hdl_netlist_block_design=6 addsrcwizard_specify_or_create_constraint_files=4 addsrcwizard_specify_simulation_specific_hdl_files=2
basedialog_cancel=10 basedialog_close=1 basedialog_ok=50 basedialog_yes=9
boardchooser_board_table=2 cmdmsgdialog_ok=1 constraintschooserpanel_add_files=2 createnewdiagramdialog_design_name=9
createsrcfiledialog_file_name=5 filesetpanel_file_set_panel_tree=369 filesetpanel_messages=3 filesetview_collapse_all=5
filesetview_expand_all=4 flownavigatortreepanel_flow_navigator_tree=40 graphicalview_zoom_fit=38 graphicalview_zoom_in=4
graphicalview_zoom_out=8 hardwaretreepanel_hardware_tree_table=1 hcodeeditor_close=1 hcodeeditor_search_text_combo_box=5
hpopuptitle_close=1 htree_collapse_all=1 instancemenu_floorplanning=1 mainmenumgr_checkpoint=3
mainmenumgr_edit=12 mainmenumgr_file=14 mainmenumgr_flow=8 mainmenumgr_help=2
mainmenumgr_ip=2 mainmenumgr_project=6 mainmenumgr_reports=4 mainmenumgr_tools=13
mainmenumgr_view=2 mainmenumgr_window=2 mainwinmenumgr_layout=2 msgtreepanel_message_severity=3
msgtreepanel_message_view_tree=211 msgview_clear_messages_resulting_from_user_executed=17 msgview_critical_warnings=1 msgview_information_messages=5
msgview_manage_message_suppression=2 msgview_warning_messages=6 openfileaction_cancel=2 opentargetwizard_connect_to=1
pacommandnames_add_sources=11 pacommandnames_auto_connect_ports=1 pacommandnames_auto_connect_target=21 pacommandnames_auto_update_hier=16
pacommandnames_create_top_hdl=1 pacommandnames_generate_composite_file=1 pacommandnames_new_project=1 pacommandnames_open_hardware_manager=5
pacommandnames_open_project=2 pacommandnames_open_target_wizard=2 pacommandnames_regenerate_layout=4 pacommandnames_run_bitgen=3
pacommandnames_set_as_top=4 pacommandnames_simulation_live_break=1 pacommandnames_simulation_live_run=3 pacommandnames_simulation_relaunch=25
pacommandnames_simulation_run_behavioral=9 pacommandnames_simulation_run_post_synthesis_functional=1 pacommandnames_src_disable=2 pacommandnames_src_enable=2
pacommandnames_toggle_view_nav=5 pacommandnames_validate_rsb_design=1 pacommandnames_zoom_fit=1 paviews_code=11
paviews_project_summary=18 paviews_schematic=2 planaheadtab_refresh_changed_modules=18 planaheadtab_refresh_ip_catalog=2
planaheadtab_show_flow_navigator=6 programdebugtab_open_target=26 programdebugtab_program_device=34 programfpgadialog_program=32
progressdialog_background=14 progressdialog_cancel=2 projectnamechooser_project_name=2 projecttab_reload=1
quickhelp_help=1 rdicommands_copy=1 rdicommands_custom_commands=3 rdicommands_delete=2
rdicommands_property_editor=2 rdicommands_settings=2 rdiviews_property_editor=1 rdiviews_waveform_viewer=733
rsbexternalportproppanels_name=5 rungadget_show_warning_and_error_messages_in_messages=1 saveprojectutils_dont_save=1 saveprojectutils_save=4
selectmenu_highlight=3 settingsdialog_options_tree=8 settingseditorpage_use_this_drop_down_list_box_to_select=1 simpleoutputproductdialog_generate_output_products_immediately=1
simulationobjectspanel_simulation_objects_tree_table=68 simulationscopespanel_simulate_scope_table=23 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3 srcchooserpanel_create_file=6
srcmenu_ip_hierarchy=14 srcmenu_open_selected_source_files=1 syntheticagettingstartedview_recent_projects=12 syntheticastatemonitor_cancel=4
systembuilderview_add_ip=1 systembuilderview_pinning=3 taskbanner_close=15 tclconsoleview_tcl_console_code_editor=1
waveformnametree_waveform_name_tree=115
java_command_handlers
addsources=9 autoconnectport=4 autoconnecttarget=20 closeproject=3
createblockdesign=1 createtophdl=1 editdelete=3 launchopentarget=2
launchprogramfpga=24 managecompositetargets=1 newproject=1 openhardwaremanager=5
openproject=2 recustomizecore=3 regeneratersblayout=4 runbitgen=15
runimplementation=4 runsynthesis=8 savefileproxyhandler=1 setsourceenabled=4
settopnode=4 showpropertyeditor=2 showview=1 simulationrelaunch=23
simulationrun=10 simulationrunfortime=2 toggleviewnavigator=4 toolssettings=2
validatersbdesign=1 viewtaskimplementation=1 viewtaskrtlanalysis=3 zoomfit=1
other_data
guimode=15
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=1 export_simulation_ies=1
export_simulation_modelsim=1 export_simulation_questa=1 export_simulation_riviera=1 export_simulation_vcs=1
export_simulation_xsim=1 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=87 simulator_language=Mixed srcsetcount=7 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=3 totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
carry4=8 fdre=188 fdse=2 gnd=2
ibuf=3 lut1=1 lut2=23 lut3=105
lut4=12 lut5=26 lut6=48 obuf=1
vcc=4
pre_unisim_transformation
carry4=8 fdre=188 fdse=2 gnd=2
ibuf=3 lut1=1 lut2=23 lut3=105
lut4=12 lut5=26 lut6=48 obuf=1
vcc=4

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

ip_statistics
Debounce_Switch/1
c_debounce_limit=250000 core_container=NA iptotal=1 x_ipcorerevision=1
x_iplanguage=VERILOG x_iplibrary=module_ref x_ipname=Debounce_Switch x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
IP_Integrator/1
bdsource=USER core_container=NA iptotal=1 maxhierdepth=0
numblks=2 numhdlrefblks=2 numhierblks=0 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=2 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=design_1
x_ipvendor=xilinx.com x_ipversion=1.00.a
uart_top/1
baud_rate=115200 clk_freq=125000000 core_container=NA iptotal=1
nbytes=12 x_ipcorerevision=1 x_iplanguage=VERILOG x_iplibrary=module_ref
x_ipname=uart_top x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-18=3

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") clocks=0.001415 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Medium
confidence_level_overall=Medium customer=TBD customer_class=TBD devstatic=0.105897
die=xc7z020clg400-1 dsp_output_toggle=12.500000 dynamic=0.002314 effective_thetaja=11.53
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=0.000097 input_toggle=12.500000 junction_temp=26.2 (C)
logic=0.000420 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.108211
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=clg400
pct_clock_constrained=1.000000 pct_inputs_defined=33 platform=lin64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000382 simulation_file=None speedgrade=-1
static_prob=False temp_grade=commercial thetajb=7.4 (C/W) thetasa=0.0 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.53 user_junc_temp=26.2 (C)
user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.010245
vccaux_total_current=0.010245 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000440
vccbram_total_current=0.000440 vccbram_voltage=1.000000 vccint_dynamic_current=0.002307 vccint_static_current=0.007420
vccint_total_current=0.009726 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000002 vcco33_static_current=0.001000
vcco33_total_current=0.001002 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000
vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000
vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000
vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.010330
vccpaux_total_current=0.010330 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.016302
vccpint_total_current=0.016302 vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.003000
vccpll_total_current=0.003000 vccpll_voltage=1.800000 version=2020.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=8
fdre_functional_category=Flop & Latch fdre_used=188 fdse_functional_category=Flop & Latch fdse_used=2
ibuf_functional_category=IO ibuf_used=3 lut1_functional_category=LUT lut1_used=1
lut2_functional_category=LUT lut2_used=23 lut3_functional_category=LUT lut3_used=105
lut4_functional_category=LUT lut4_used=12 lut5_functional_category=LUT lut5_used=26
lut6_functional_category=LUT lut6_used=48 obuf_functional_category=IO obuf_used=1
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=147 lut_as_logic_util_percentage=0.28
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=190 register_as_flip_flop_util_percentage=0.18
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=147 slice_luts_util_percentage=0.28
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=190 slice_registers_util_percentage=0.18
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=147 lut_as_logic_util_percentage=0.28 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=11 lut_in_front_of_the_register_is_used_fixed=11 lut_in_front_of_the_register_is_used_used=0
register_driven_from_outside_the_slice_fixed=0 register_driven_from_outside_the_slice_used=11 register_driven_from_within_the_slice_fixed=11 register_driven_from_within_the_slice_used=179
slice_available=13300 slice_fixed=0 slice_registers_available=106400 slice_registers_fixed=0
slice_registers_used=190 slice_registers_util_percentage=0.18 slice_used=60 slice_util_percentage=0.45
slicel_fixed=0 slicel_used=45 slicem_fixed=0 slicem_used=15
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_used=8 unique_control_sets_util_percentage=0.06
using_o5_and_o6_fixed=0.06 using_o5_and_o6_used=68 using_o5_output_only_fixed=68 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=79
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7z020clg400-1 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:17s hls_ip=0 memory_gain=0.000MB memory_peak=2158.617MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::