Sommatore Project Status | |||
Project File: | boundscan.xise | Parser Errors: | No Errors |
Module Name: | boundscan | Implementation State: | Placed and Routed |
Target Device: | xc3s1200e-4fg320 |
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No Errors |
Product Version: | ISE 14.1 |
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11 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slices containing only related logic | 0 | 0 | 0% | ||
Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
Number of bonded IOBs | 11 | 250 | 4% | ||
IOB Latches | 5 | ||||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 1.00 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | ven 15. nov 15:08:54 2013 | 0 | 11 Warnings (0 new) | 0 | |
Translation Report | Current | ven 15. nov 15:08:59 2013 | 0 | 0 | 0 | |
Map Report | Current | ven 15. nov 15:09:04 2013 | 0 | 0 | 3 Infos (0 new) | |
Place and Route Report | Current | ven 15. nov 15:09:16 2013 | 0 | 0 | 1 Info (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | ven 15. nov 15:09:19 2013 | 0 | 0 | 6 Infos (0 new) | |
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | ven 15. nov 17:19:44 2013 |