#include "config.h"
Go to the source code of this file.
Defines | |
#define | MSK_SPI_MODE ((1<<CPOL)|(1<<CPHA)) |
#define | MSK_SPI_CPHA_LEADING (0<<CPHA) |
#define | MSK_SPI_CPHA_TRAILING (1<<CPHA) |
#define | MSK_SPI_CPOL_LOW (0<<CPOL) |
#define | MSK_SPI_CPOL_HIGH (1<<CPOL) |
#define | SPI_MODE_0 (MSK_SPI_CPOL_LOW|MSK_SPI_CPHA_LEADING) |
#define | SPI_MODE_1 (MSK_SPI_CPOL_LOW|MSK_SPI_CPHA_TRAILING) |
#define | SPI_MODE_2 (MSK_SPI_CPOL_HIGH|MSK_SPI_CPHA_LEADING) |
#define | SPI_MODE_3 (MSK_SPI_CPOL_HIGH|MSK_SPI_CPHA_TRAILING) |
#define | MSK_SPI_MULT2 0x80 |
#define | MSK_SPR ((1<<SPR1)|(1<<SPR0)) |
#define | MSK_SPI_DIV4 ((0<<SPR1)|(0<<SPR0)) |
#define | MSK_SPI_DIV16 ((0<<SPR1)|(1<<SPR0)) |
#define | MSK_SPI_DIV64 ((1<<SPR1)|(0<<SPR0)) |
#define | MSK_SPI_DIV128 ((1<<SPR1)|(1<<SPR0)) |
#define | SPI_RATE_0 (MSK_SPI_MULT2|MSK_SPI_DIV4) |
#define | SPI_RATE_1 (MSK_SPI_DIV4) |
#define | SPI_RATE_2 (MSK_SPI_MULT2|MSK_SPI_DIV16) |
#define | SPI_RATE_3 (MSK_SPI_DIV16) |
#define | SPI_RATE_4 (MSK_SPI_MULT2|MSK_SPI_DIV64) |
#define | SPI_RATE_5 (MSK_SPI_DIV64) |
#define | SPI_RATE_6 (MSK_SPI_DIV128) |
#define | Spi_enable() (SPCR |= (1<<SPE)) |
#define | Spi_disable() (SPCR &= ~(1<<SPE)) |
#define | Spi_enable_it() (SPCR |= (1<<SPIE)) |
#define | Spi_disable_it() (SPCR &= ~(1<<SPIE)) |
#define | Spi_select_slave() (SPCR &= ~(1<<MSTR)) |
#define | Spi_select_master() (SPCR |= (1<<MSTR)) |
#define | Spi_set_lsbfirst() (SPCR |= (1<<DORD)) |
#define | Spi_set_msbfirst() (SPCR &= ~(1<<DORD)) |
#define | Spi_set_mode(mode) {SPCR &= ~MSK_SPI_MODE; SPCR |= mode;} |
#define | Spi_set_rate(rate) {SPCR &= ~MSK_SPR; SPCR |= rate&MSK_SPR; (rate & MSK_SPI_MULT2)? Spi_set_doublespeed() : Spi_clear_doublespeed();} |
#define | Spi_set_doublespeed() (SPSR |= (1<<SPI2X)) |
#define | Spi_clear_doublespeed() (SPSR &= ~(1<<SPI2X)) |
#define | Spi_init_bus() ((DDRB |= (1<<DDB2)|(1<<DDB1))) |
#define | Spi_disable_ss() |
#define | Spi_enble_ss() |
#define | Spi_wait_spif() while ((SPSR & (1<<SPIF)) == 0) |
#define | Spi_wait_eor() while ((SPSR & (1<<SPIF)) == 0) |
#define | Spi_wait_eot() while ((SPSR & (1<<SPIF)) == 0) |
#define | Spi_eor() ((SPSR & (1<<SPIF)) == (1<<SPIF)) |
#define | Spi_eot() ((SPSR & (1<<SPIF)) == (1<<SPIF)) |
#define | Spi_is_colision() (SPSR&(1<<WCOL)) |
#define | Spi_get_byte() (SPDR) |
#define | Spi_tx_ready() (SPSR & (1<<SPIF)) |
#define | Spi_rx_ready() Spi_tx_ready() |
#define | Spi_ack_read() (SPSR) |
#define | Spi_ack_write() (SPDR) |
#define | Spi_ack_cmd() (SPSR) |
#define | Spi_read_data() (SPDR) |
#define | Spi_write_data(byte) {(SPDR=byte);Spi_wait_spif();} |
Definition in file spi_drv.h.
#define SPI_MODE_0 (MSK_SPI_CPOL_LOW|MSK_SPI_CPHA_LEADING) |
#define SPI_MODE_1 (MSK_SPI_CPOL_LOW|MSK_SPI_CPHA_TRAILING) |
#define SPI_MODE_2 (MSK_SPI_CPOL_HIGH|MSK_SPI_CPHA_LEADING) |
#define SPI_MODE_3 (MSK_SPI_CPOL_HIGH|MSK_SPI_CPHA_TRAILING) |
#define SPI_RATE_0 (MSK_SPI_MULT2|MSK_SPI_DIV4) |
#define Spi_enable | ( | ) | (SPCR |= (1<<SPE)) |
#define Spi_select_master | ( | ) | (SPCR |= (1<<MSTR)) |
#define Spi_set_mode | ( | mode | ) | {SPCR &= ~MSK_SPI_MODE; SPCR |= mode;} |
#define Spi_set_rate | ( | rate | ) | {SPCR &= ~MSK_SPR; SPCR |= rate&MSK_SPR; (rate & MSK_SPI_MULT2)? Spi_set_doublespeed() : Spi_clear_doublespeed();} |
#define Spi_init_bus | ( | ) | ((DDRB |= (1<<DDB2)|(1<<DDB1))) |
#define Spi_disable_ss | ( | ) |
#define Spi_ack_write | ( | ) | (SPDR) |
Definition at line 112 of file spi_drv.h.
Referenced by df_host_write_sector(), df_read_open(), df_wait_busy(), df_write_close(), df_write_open(), df_write_sector(), df_write_sector_from_ram(), and mmc_sd_write_sector().
#define Spi_read_data | ( | ) | (SPDR) |
Definition at line 116 of file spi_drv.h.
Referenced by df_host_read_sector(), df_mem_check(), df_read_sector(), df_read_sector_2_ram(), df_wait_busy(), mmc_sd_get_cid(), mmc_sd_get_csd(), mmc_sd_read_sector(), mmc_sd_read_sector_to_ram(), mmc_sd_send_and_read(), and mmc_sd_write_sector().
#define Spi_write_data | ( | byte | ) | {(SPDR=byte);Spi_wait_spif();} |
Definition at line 117 of file spi_drv.h.
Referenced by df_host_read_sector(), df_host_write_sector(), df_mem_check(), df_read_open(), df_read_sector(), df_read_sector_2_ram(), df_wait_busy(), df_write_close(), df_write_open(), df_write_sector(), df_write_sector_from_ram(), mmc_sd_check_presence(), mmc_sd_command(), mmc_sd_erase_sector_group(), mmc_sd_get_cid(), mmc_sd_get_csd(), mmc_sd_get_status(), mmc_sd_init(), mmc_sd_lock_operation(), mmc_sd_read_sector(), mmc_sd_read_sector_to_ram(), mmc_sd_send_and_read(), mmc_sd_write_sector(), and mmc_sd_write_sector_from_ram().