power_drv.h

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00016 
00017 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
00018  *
00019  * Redistribution and use in source and binary forms, with or without
00020  * modification, are permitted provided that the following conditions are met:
00021  *
00022  * 1. Redistributions of source code must retain the above copyright notice,
00023  * this list of conditions and the following disclaimer.
00024  *
00025  * 2. Redistributions in binary form must reproduce the above copyright notice,
00026  * this list of conditions and the following disclaimer in the documentation
00027  * and/or other materials provided with the distribution.
00028  *
00029  * 3. The name of Atmel may not be used to endorse or promote products derived
00030  * from this software without specific prior written permission.
00031  *
00032  * 4. This software may only be redistributed and used in connection with an Atmel
00033  * AVR product.
00034  *
00035  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
00036  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00037  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND
00038  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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00040  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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00044  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045  */
00046 
00047 
00048 #ifndef _POWER_DRV_H_
00049 #define _POWER_DRV_H_
00050 
00051 #ifdef  __GNUC__
00052    #include <avr/power.h>
00053    
00054    #if (__AVR_LIBC_VERSION__<=10602UL) //for AVRLIBC bug #23871 : clock_prescale_set() not available for ATmega32U4
00055    typedef enum
00056    {
00057        clock_div_1 = 0,
00058        clock_div_2 = 1,
00059        clock_div_4 = 2,
00060        clock_div_8 = 3,
00061        clock_div_16 = 4,
00062        clock_div_32 = 5,
00063        clock_div_64 = 6,
00064        clock_div_128 = 7,
00065        clock_div_256 = 8
00066    } clock_div_t;
00067 
00068    #define clock_prescale_set(x) \
00069    { \
00070            uint8_t tmp = _BV(CLKPCE); \
00071            __asm__ __volatile__ ( \
00072                    "in __tmp_reg__,__SREG__" "\n\t" \
00073                    "cli" "\n\t" \
00074                    "sts %1, %0" "\n\t" \
00075                    "sts %1, %2" "\n\t" \
00076                    "out __SREG__, __tmp_reg__" \
00077                    : /* no outputs */ \
00078                    : "d" (tmp), \
00079                      "M" (_SFR_MEM_ADDR(CLKPR)), \
00080                      "d" (x) \
00081                    : "r0"); \
00082    }
00083 
00084 
00085    #define clock_prescale_get()  (clock_div_t)(CLKPR & (uint8_t)((1<<CLKPS0)|(1<<CLKPS1)|(1<<CLKPS2)|(1<<CLKPS3)))
00086 
00087    #endif
00088 
00089 
00090 #endif
00094 
00095 //_____ M A C R O S ________________________________________________________
00096 
00097 #define Setup_idle_mode()                        (SMCR=0,SMCR |= (1<<SE))
00098 #define Setup_power_down_mode()                   (SMCR=0,SMCR |= (1<<SE)+(1<<SM1))
00099 #define Setup_adc_noise_reduction_mode()         (SMCR=0,SMCR |= (1<<SE)+(1<<SM0))
00100 #define Setup_power_save_mode()                  (SMCR=0,SMCR |= (1<<SE)+(1<<SM1)+(1<<SM0))
00101 #define Setup_standby_mode()                     (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1))
00102 #define Setup_ext_standby_mode()                  (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1)+(1<<SM0))
00103 
00113 #ifdef  __GNUC__
00114    #define Clear_prescaler()                       (clock_prescale_set(0))
00115 #else
00116    #define Clear_prescaler()                       (Set_cpu_prescaler(0))
00117 #endif
00118 
00128 #ifdef  __GNUC__
00129    #define Set_cpu_prescaler(x)                        (clock_prescale_set(x))
00130 #else
00131    extern void Set_cpu_prescaler(U8 x);
00132 #endif
00133 
00134 
00135 #define Sleep_instruction()              {asm("SLEEP");}
00136 
00137 //Backward compatibility
00138 #define Set_power_down_mode()              set_power_down_mode()
00139 #define Set_idle_mode()            set_idle_mode()
00140 
00141 //_____ D E C L A R A T I O N ______________________________________________
00142 
00143 void set_idle_mode(void);
00144 void set_power_down_mode(void);
00145 void set_adc_noise_reduction_mode(void);
00146 void set_power_save_mode(void);
00147 void set_standby_mode(void);
00148 void set_ext_standby_mode(void);
00149 
00158 #define Enter_idle_mode()                 (set_idle_mode())
00159 
00168 #define Enter_power_down_mode()           (set_power_down_mode())
00169 
00178 #define Enter_adc_noise_reduction_mode()  (set_adc_noise_reduction_mode())
00179 
00188 #define Enter_power_save_mode()           (set_power_save_mode())
00189 
00198 #define Enter_standby_mode()              (set_standby_mode())
00199 
00208 #define Enter_ext_standby_mode()          (set_ext_standby_mode())
00209 
00210 
00212 
00213 
00214 
00215 
00219 
00220 //_____ M A C R O S ________________________________________________________
00221 
00222 // Clock control
00223 #define   Enable_external_clock()       (CLKSEL0 |= (1<<EXTE))
00224 #define   Disable_external_clock()      (CLKSEL0 &= ~(1<<EXTE))
00225 #define   Enable_RC_clock()             (CLKSEL0 |= (1<<RCE))
00226 #define   Disable_RC_clock()            (CLKSEL0 &= ~(1<<RCE))
00227 
00228 // Clock state
00229 #define   External_clock_ready()        (((CLKSTA&(1<<EXTON)) != 0) ? TRUE : FALSE)
00230 #define   RC_clock_ready()              (((CLKSTA&(1<<RCON)) != 0) ? TRUE : FALSE)
00231 
00232 // Clock selection
00233 #define   Select_external_clock()       (CLKSEL0 |= (1<<CLKS))
00234 #define   Select_RC_clock()             (CLKSEL0 &= ~(1<<CLKS))
00235 
00236 // Clock settings : when using a clock source, only the other clock source setting can be modified
00237 // Set the source setting of the next clock source to use before switching to it
00238 #define   Load_ext_clock_config(cfg)    (CLKSEL1 = (CLKSEL1&0xF0) | ((cfg&0x0F)<<EXCKSEL0), \
00239                                          CLKSEL0 = (CLKSEL0&0xCF) | (((cfg&0x30)>>4)<<EXSUT0))
00240 
00241 #define   Load_RC_clock_config(cfg)     (CLKSEL1 = (CLKSEL1&0x0F) | ((cfg&0x0F)<<RCCKSEL0), \
00242                                          CLKSEL0 = (CLKSEL0&0x3F) | (((cfg&0x30)>>4)<<RCSUT0))
00243 
00244 //_____ C L O C K   D E F I N I T I O N S ______________________________________
00245 // Configuration byte defined as SUT<1:0> & CKSEL<3:0> (CKSEL0 is the LSb)
00246 
00247 // Interal RC oscillator (frequency between 7.3 and 8.1 MHz)
00248 #define   OSC_INTRC_0MS                  0x02
00249 #define   OSC_INTRC_4MS                  0x12
00250 #define   OSC_INTRC_65MS                 0x22
00251 
00252 // External crystal, frequency between 0.3 and 0.9 MHz
00253 #define   OSC_XTAL_RANGE1_258CK_4MS      0x08
00254 #define   OSC_XTAL_RANGE1_258CK_65MS     0x18
00255 #define   OSC_XTAL_RANGE1_1KCK_0MS       0x28
00256 #define   OSC_XTAL_RANGE1_1KCK_4MS       0x38
00257 #define   OSC_XTAL_RANGE1_1KCK_65MS      0x09
00258 #define   OSC_XTAL_RANGE1_16KCK_0MS      0x19
00259 #define   OSC_XTAL_RANGE1_16KCK_4MS      0x29
00260 #define   OSC_XTAL_RANGE1_16KCK_65MS     0x39
00261 
00262 // External crystal, frequency between 0.9 and 3 MHz
00263 #define   OSC_XTAL_RANGE2_258CK_4MS      0x0A
00264 #define   OSC_XTAL_RANGE2_258CK_65MS     0x1A
00265 #define   OSC_XTAL_RANGE2_1KCK_0MS       0x2A
00266 #define   OSC_XTAL_RANGE2_1KCK_4MS       0x3A
00267 #define   OSC_XTAL_RANGE2_1KCK_65MS      0x0B
00268 #define   OSC_XTAL_RANGE2_16KCK_0MS      0x1B
00269 #define   OSC_XTAL_RANGE2_16KCK_4MS      0x2B
00270 #define   OSC_XTAL_RANGE2_16KCK_65MS     0x3B
00271 
00272 // External crystal, frequency between 3 and 8 MHz
00273 #define   OSC_XTAL_RANGE3_258CK_4MS      0x0C
00274 #define   OSC_XTAL_RANGE3_258CK_65MS     0x1C
00275 #define   OSC_XTAL_RANGE3_1KCK_0MS       0x2C
00276 #define   OSC_XTAL_RANGE3_1KCK_4MS       0x3C
00277 #define   OSC_XTAL_RANGE3_1KCK_65MS      0x0D
00278 #define   OSC_XTAL_RANGE3_16KCK_0MS      0x1D
00279 #define   OSC_XTAL_RANGE3_16KCK_4MS      0x2D
00280 #define   OSC_XTAL_RANGE3_16KCK_65MS     0x3D
00281 
00282 // External crystal, frequency between 8 and 16 MHz
00283 #define   OSC_XTAL_RANGE4_258CK_4MS      0x0E
00284 #define   OSC_XTAL_RANGE4_258CK_65MS     0x1E
00285 #define   OSC_XTAL_RANGE4_1KCK_0MS       0x2E
00286 #define   OSC_XTAL_RANGE4_1KCK_4MS       0x3E
00287 #define   OSC_XTAL_RANGE4_1KCK_65MS      0x0F
00288 #define   OSC_XTAL_RANGE4_16KCK_0MS      0x1F
00289 #define   OSC_XTAL_RANGE4_16KCK_4MS      0x2F
00290 #define   OSC_XTAL_RANGE4_16KCK_65MS     0x3F
00291 
00292 // External clock
00293 #define   OSC_EXTCLK_0MS                 0x00
00294 #define   OSC_EXTCLK_4MS                 0x10
00295 #define   OSC_EXTCLK_65MS                0x20
00296 
00297 
00298 //_____ D E C L A R A T I O N ______________________________________________
00299 
00300 void Clock_switch_external(void);
00301 void Clock_switch_internal(void);
00302 
00304 
00305 
00306 #endif  // _POWER_DRV_H_
00307 

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