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00041 #ifndef _SPI_DRV_H_
00042 #define _SPI_DRV_H_
00043
00044
00045
00046 #include "config.h"
00047
00048
00049
00050
00051
00052 #define MSK_SPI_MODE ((1<<CPOL)|(1<<CPHA))
00053 #define MSK_SPI_CPHA_LEADING (0<<CPHA)
00054 #define MSK_SPI_CPHA_TRAILING (1<<CPHA)
00055 #define MSK_SPI_CPOL_LOW (0<<CPOL)
00056 #define MSK_SPI_CPOL_HIGH (1<<CPOL)
00057 #define SPI_MODE_0 (MSK_SPI_CPOL_LOW|MSK_SPI_CPHA_LEADING)
00058 #define SPI_MODE_1 (MSK_SPI_CPOL_LOW|MSK_SPI_CPHA_TRAILING)
00059 #define SPI_MODE_2 (MSK_SPI_CPOL_HIGH|MSK_SPI_CPHA_LEADING)
00060 #define SPI_MODE_3 (MSK_SPI_CPOL_HIGH|MSK_SPI_CPHA_TRAILING)
00061
00062
00063 #define MSK_SPI_MULT2 0x80
00064 #define MSK_SPR ((1<<SPR1)|(1<<SPR0))
00065 #define MSK_SPI_DIV4 ((0<<SPR1)|(0<<SPR0))
00066 #define MSK_SPI_DIV16 ((0<<SPR1)|(1<<SPR0))
00067 #define MSK_SPI_DIV64 ((1<<SPR1)|(0<<SPR0))
00068 #define MSK_SPI_DIV128 ((1<<SPR1)|(1<<SPR0))
00069 #define SPI_RATE_0 (MSK_SPI_MULT2|MSK_SPI_DIV4) // Fper / 2
00070 #define SPI_RATE_1 (MSK_SPI_DIV4) // Fper / 4
00071 #define SPI_RATE_2 (MSK_SPI_MULT2|MSK_SPI_DIV16) // Fper / 8
00072 #define SPI_RATE_3 (MSK_SPI_DIV16) // Fper / 16
00073 #define SPI_RATE_4 (MSK_SPI_MULT2|MSK_SPI_DIV64) // Fper / 32
00074 #define SPI_RATE_5 (MSK_SPI_DIV64) // Fper / 64
00075 #define SPI_RATE_6 (MSK_SPI_DIV128) // Fper / 128
00076
00077
00078
00079
00080
00081 #define Spi_enable() (SPCR |= (1<<SPE))
00082 #define Spi_disable() (SPCR &= ~(1<<SPE))
00083
00084
00085 #define Spi_enable_it() (SPCR |= (1<<SPIE))
00086 #define Spi_disable_it() (SPCR &= ~(1<<SPIE))
00087
00088
00089 #define Spi_select_slave() (SPCR &= ~(1<<MSTR))
00090 #define Spi_select_master() (SPCR |= (1<<MSTR))
00091 #define Spi_set_lsbfirst() (SPCR |= (1<<DORD))
00092 #define Spi_set_msbfirst() (SPCR &= ~(1<<DORD))
00093 #define Spi_set_mode(mode) {SPCR &= ~MSK_SPI_MODE; SPCR |= mode;}
00094 #define Spi_set_rate(rate) {SPCR &= ~MSK_SPR; SPCR |= rate&MSK_SPR; (rate & MSK_SPI_MULT2)? Spi_set_doublespeed() : Spi_clear_doublespeed();}
00095 #define Spi_set_doublespeed() (SPSR |= (1<<SPI2X))
00096 #define Spi_clear_doublespeed() (SPSR &= ~(1<<SPI2X))
00097 #define Spi_init_bus() ((DDRB |= (1<<DDB2)|(1<<DDB1)))
00098 #define Spi_disable_ss()
00099 #define Spi_enble_ss()
00100
00101
00102 #define Spi_wait_spif() while ((SPSR & (1<<SPIF)) == 0) // for any SPI_RATE_x
00103 #define Spi_wait_eor() while ((SPSR & (1<<SPIF)) == 0) // wait end of reception
00104 #define Spi_wait_eot() while ((SPSR & (1<<SPIF)) == 0) // wait end of transmission
00105 #define Spi_eor() ((SPSR & (1<<SPIF)) == (1<<SPIF)) // check end of reception
00106 #define Spi_eot() ((SPSR & (1<<SPIF)) == (1<<SPIF)) // check end of transmission
00107 #define Spi_is_colision() (SPSR&(1<<WCOL))
00108 #define Spi_get_byte() (SPDR)
00109 #define Spi_tx_ready() (SPSR & (1<<SPIF))
00110 #define Spi_rx_ready() Spi_tx_ready()
00111 #define Spi_ack_read() (SPSR)
00112 #define Spi_ack_write() (SPDR)
00113 #define Spi_ack_cmd() (SPSR)
00114
00115
00116 #define Spi_read_data() (SPDR)
00117 #define Spi_write_data(byte) {(SPDR=byte);Spi_wait_spif();}
00118
00119 #endif // _SPI_DRV_H_
00120