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D flip-flop in frequency divider

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spicer

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high speed low noise divider

I want to know how to design a high speed(up to 800MHz) D flip-flop in frequency divider. And I also want to know if this D flip-flop need a reset port. Can some one help me? Thank you in advance.
 

frequency divider d flip-flop

spicer said:
I want to know how to design a high speed(up to 800MHz) D flip-flop in frequency divider. And I also want to know if this D flip-flop need a reset port. Can some one help me? Thank you in advance.
Click to expand...

hi
the simplest way is to use the standard cells your foundry provides.
whether reset or set ports are needed depends your programmable divider.
jeff
 

cml high speed d-flipflop

In the case of high speed,you can consider using the Currert Mode Logic.

Here are some paper that might help you.
 

how a d flip flop works as a divider

jfyan said:
spicer said:
I want to know how to design a high speed(up to 800MHz) D flip-flop in frequency divider. And I also want to know if this D flip-flop need a reset port. Can some one help me? Thank you in advance.
Click to expand...

hi
the simplest way is to use the standard cells your foundry provides.
whether reset or set ports are needed depends your programmable divider.
jeff
Click to expand...

Flip-flops used from standard cells may not be able to work at this frequency , you must check it well before using it.
The need for a reset port depends on the type of counter you are using and the stand-by power consumption you are targetting.
 

frequency divider d flip flops

You can use CML DFFs or TSPC DFFs to gain high speed. All of this are describled in RF Microelectronics of Razavi.
 

d flip flop frequency divider

800MHz is not such a high frequency. U need not go to CML for that... Of course it depends on technology. But my gut feeling is that CML is not needed.

By the look of it, u r trying to design a custom flop. A simple Master-Slave model (containing transmission gates as controlled switches) should be fine for the frequency u r aiming at.. Size the transmission gates properly to get good setup/hold times.

Requirement for a reset/preset depends on the usage of the flop. If you are using it for clocking out data or used in a register, then its a good idea to have reset. If you are just using it to latch some info then reset may not be needed.

Hope this helps..
 

d flip-flop frequency divider

you should use CML structure.
 

digital frequency divider dff

laglead said:
you should use CML structure.
Click to expand...

Why "should"???
I have designed a custom flop which works till 2GHz in 130nm technology with normal logic only. That is the reason I said it depends on technology..

It is NOT compulsory to use CML here..
 

cml tspc

I second not using CML if you can. CML back to CMOS at high speed take up lots of power and is another complication.
 

cml divider tspc divider

I used TSPC in my design and it worked well in frequencies larger than 8oo MHz, it is simple unlike CML, so I advise to use TSPC.
but I have another problem that my design requires DFF that works in 2.4 GHz and TSPC didn't work well in this frequencies and all designs tried (including CML) don't although it is stated in the papers that they can work for this frequency.
I know I'm missing some thing in providing siutable values for W & L but some one experience to tell me what to do??
 

flip flop divider

What is the technology that you are using?
 

devider dflipflop

I'm using TSMC(0.13 u)
can I reach such high frequency using this technology??
 

divider flipflop

Yes it's possible to go above 2.4G in TSMC .13. I've done TSPC divider that went up to around 4.5G (before layout-extraction low-vt option.) Of course, if you are trying to use it as a generic D-FF with logic between the D-FFs, that's another story....
 

d flip flop divider

ahmed tolba said:
I'm using TSMC(0.13 u)
can I reach such high frequency using this technology??
Click to expand...

If you are using a low vt process, it should definitely be possible...
 

frequency divider flip

TSPC is a good choice
 

is it possibe in 0.18um technology to give a clock of 6GHz. I am trying to design a frequency synthesizer which operates at 6Ghz.
 

yeah 0.18 ring oscillaotr can give u this speed 6 GHz , even u can get more with LC

and u can use the CML logic to do a dividers , but it will be good experince

khouly
 

CML is certainly not neccessary, reasonable (<say sub 1024 division ration) freq. dividers can easily be built out of plain vanilla CMOS logic and standard master slave flops and work at 800MHz even in 0.18, not to mention 0.13.

CML might have advantages in the dividers if you are after extremely low jitter and your loop BW is is very low since it is a very low noise topology (almost no switching noise since it always sinks the same current, even during value changes, this makes it very high power though).
 

khouly said:
yeah 0.18 ring oscillaotr can give u this speed 6 GHz , even u can get more with LC

and u can use the CML logic to do a dividers , but it will be good experince

khouly
Click to expand...

thanks for ur suggestion. ok to be precise i am designing a Direct digital frequency synthesizer. I need a clock of 6Ghz for its operation. Would i Still be able to do it with a ring oscillator?? i was trying to design a flip flop and then subsequently a regsiter to operate at 6GHz. but the maximum i cud get is 1.25-2Ghz..
 

u need to generate the clock , or just want to design the filpflop

khouly
 

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