module top (clk, out);
input clk;
reg [3:0] count = 0;
wire [8:0] path;
output out;
always @ (posedge clk)
count <= count + 1;
assign path[0] = count[3];
assign out = path[8];
genvar n;
generate
for (n=0; n<=7; n=n+1) begin : flops
dflop u (.clk(clk), .in(path[n]), .out(path[n+1]));
end
endgenerate
endmodule
module dflop (clk, in, out);
input clk, in;
output reg out;
always @ (posedge clk)
out <= in;
endmodule
// bad loop - won't synthesize properly in Xilinx XST 9.1i, or Cadence Buildgates
genvar g;
generate for ( x=7; x > 0; x=x-1 ) begin : bad_loop
if ( x == 7 )
assign my_signal[x] = my_input;
else
assign my_signal[x] = ^my_signal[7:x+1]; // composite-XOR
endassign my_signal[7] = my_input; // = my_input
assign my_signal[6] = ^my_signal[7:7]; // = my_input
assign my_signal[5] = ^my_signal[7:6]; // = zero
assign my_signal[4] = ^my_signal[7:5]; // = zero
assign my_signal[3] = ^my_signal[7:4]; // = zero
assign my_signal[2] = ^my_signal[7:3]; // = zero
assign my_signal[1] = ^my_signal[7:2]; // = zeromodule top (my_input, my_signal);
input my_input;
output [7:1] my_signal;
genvar x;
generate
for ( x=7; x > 0; x=x-1 ) begin : bad_loop
if ( x == 7 )
assign my_signal[x] = my_input;
else
assign my_signal[x] = ^my_signal[7:x+1]; // composite-XOR
end
endgenerate
endmoduletypedef enum int {
TARGET_A = 0,
TARGET_B = 1,
TARGET_C = 2
} et_target;
module haha #(
parameter et_target target = TARGET_A
) (
input logic [7:0] x,
input logic [7:0] y,
output logic [7:0] z
);
// yet ... another ... silly ... example ...
generate
if ( target == TARGET_A ) begin : gen_target_a
logic [7:0] x1, y1; // <-- sometimes causes
// A ltera Quartus-II 7.1 to crash!
assign x1 = ~x;
assign y1 = {y,y}>>1; // rotate-right 1-bit
assign z = x1 + y1;
end // : gen_target_a
if ( target == TARGET_B ) begin : gen_target_b
assign z = x + y;
end // : gen_target_a
endgenerate
endmodule // : haha
