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Clock operating frequency of USB2.0 Phy in high speed and full speed modes

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bitblue

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Hi friends,

I wanna ask a question about the design of USB2.0 Phy. We know that the USB Phy can sample the 480Mb/s (high speed mode) and the 12Mb/s (full speed mode) serial data using two CDR circuits, and the the recoverred data rate has not been changed out of the CDR circuits. Then the 480Mb/s data flow into the elastic buffer to cross different timing domain. My question is what the clock operating frequency of the high speed data in the decoder, deserilizator? what about the full speed mode? because the 8bit-parallel data output's frequency is 60MHz, whether the decoder..'s is also 60Mhz.

Thanks for help in advance
 

Re: USB2.0 Phy

bitblue said:
Hi friends,

I wanna ask a question about the design of USB2.0 Phy. We know that the USB Phy can sample the 480Mb/s (high speed mode) and the 12Mb/s (full speed mode) serial data using two CDR circuits, and the the recoverred data rate has not been changed out of the CDR circuits. Then the 480Mb/s data flow into the elastic buffer to cross different timing domain. My question is what the clock operating frequency of the high speed data in the decoder, deserilizator? what about the full speed mode? because the 8bit-parallel data output's frequency is 60MHz, whether the decoder..'s is also 60Mhz.

Thanks for help in advance
Click to expand...

You shall swithc the clock frequency according to the interface mode!
 

Re: USB2.0 Phy

Basically receiving mode in digital part(not include DLL and elastic buffer) works at 60MHz at 8bit mode. Once analog part receives data with 480MHz clock rate and the DLL makes sync to the 480 MHz clock and save to elastic buffer.
The elastic buffer dumps out with 60MHz clock to digital.
 

USB2.0 Phy

I am also learning USB phy design, give more answer ,please !
 

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