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What is the Distributed RAM ?

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yasser_shoukry

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What is the Distributed RAM ? What can i do with it and what can not do with it ?

Thanks in advance
 

what is distributed ram

This is Xilinx's patent technique.

All Xilinx's FPGAs have the "Distributed RAM",
that is, each LUT can be configured as a 16*1bit RAM , ROM, LUT or 16bit shift register.

On the contrary, Altera's FPGA's LUT can only be configured as a 16bit distributed ROM.
 

distributed ram xilinx

I think your explanation is literal. Would you like to tell me why we need RAM, ROM or 16bit shift register in FPGA. I think LUT can be considered as a function generater. But does it can store the funcation itself? I'm quite confused about the functionality of the each part in the FPGA.
 

xilinx distributed ram

RAMs, ROMs, and shift registers are common building blocks for digital systems. Having them available inside the FPGA makes it easier for us to design a digital system into an FPGA.

The FPGA LUT (look-up table) is a small ROM with several address inputs and one data output. A common size is 16x1 bit, it has four inputs and one output. By setting the proper bits in that ROM, it becomes any desired boolean logic function having up to four inputs and one output. That's why it is sometimes called a function generator.

An FPGA contains thousands of these small LUTs. The LUT ROM bits are set when you load the configuration bitstream into the FPGA. They are lost if you power-down the FPGA.
 
xilinx distributed memory

The other explanation of distributed RAM is it is distributed all over FPGA. So LUTS can be used as storage i.e as RAM or ROM apart from the dedicated memory blocks which is called block RAM's.
Normally if u want smaller memories u tend to infer distributed memory then BLOCK memory because block ram sizes are fixed normally 18K Bits and it will be wasted when inferring a smaller memory.
 

how to configure lut to ram vhdl template

Thank you all, but i have some more questions to make this thing clear.
1-As i understood from your clarification is "Distributed RAM" is a functionality for optimization , so that a shift register for example instead of using many LUTs it will configure one LUT as a shift register . Am i right ??

2-Is distributed RAM functionality applied to modules or to signals or what?

3-How can I tell the synthesis to use the distributed RAM functionality ? or does the synthesis tool make it automatically ??

Thanks a lot guys.
 

distributed ram

You are using Xilinx FPGAs, correct? In most modern Xilinx FPGAs, each 16-bit LUT can be independently configured to operate in one of three modes:

1. As a 16-bit ROM. This is useful for generating a boolean logic function, or for holding a small table of data constants like an ordinary ROM.

2. As a 16-bit Distributed RAM. This is useful for read/write storage of small amounts of data. It is called "distributed" because it is normally spread out over many LUTs. For example, a 32x8 bit Distributed RAM would consume 16 LUTs.

3. As a serial-in serial-out shift register of length 1 to 16. This is useful for delaying a signal without consuming any regular flip-flops.

Some FPGAs don't provide all three modes in all LUTs.

In most projects, you don't have to worry about configuring any of that stuff because the synthesizer can do it for you. For example, if your HDL contains combinatorial logic or a table of constants, the synthesizer will automatically configure some LUTs as function generators or ROMs. If your HDL contains a small array of read/write registers, the synthesizer will automatically configure some LUTs as Distributed RAM. (If your ROM or RAM is relatively large, the synthesizer will normally use a space-saving Block ROM/RAM instead of Distributed ROM/RAM.) If your HDL contains small shift register delays, the synthesizer will automatically configure some LUTs as shift registers.

That automatic synthesizer behavior is called "inference". If you don't like the synthesizer's default behavior, or if the synthesizer isn't selecting the modes you expected, refer to chapter "HDL Coding Techniques" in your XST User Guide. If that doesn't help, you can override the behavior by specifying constraints (see your Constraints Guide), or by "instantiating" library parts that force the logic to be created a certain way (see your Libraries Guide). For example, the RAM_STYLE constraint lets your force either Block RAM or Distributed RAM.

You have probably noticed that those Guides add up to thousands of pages. Don't try to learn it all at once. ;)
 
ram distributed

a distributed ram can be easily understood if u know a little bit about architecture of fpga......it consists of slices(reference to xilinx)......and each slice contains lut's and flops where bit values can be stored....so if ur code infers these storage elements as ram then it is called a distributed ram as the storage elements r spread all over the silicon space...........it can be disadvantageous in inferring large memories because a lot of delay could be induced because of interconnect and routing delays......
 

infer distributed ram

A little something I would like to add here is that with Xilinx you cant actually infer Distributed RAM automatically hoping the Synthesis tool will do everything for you, infact your code should be in a particular format for inferring them. For eg to instantiate a single port Dist RAM your code should be like this

Code: 
   parameter RAM_WIDTH = <ram_width>;
   parameter RAM_ADDR_BITS = <ram_addr_bits>;

   reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];

   wire [RAM_WIDTH-1:0] <output_data>;

   <reg_or_wire> [RAM_ADDR_BITS-1:0] <address>;
   <reg_or_wire> [RAM_WIDTH-1:0] <input_data>;

   always @(posedge <clock>)
      if (<write_enable>)
         <ram_name>[<address>] <= <input_data>;

   assign <output_data> = <ram_name>[<address>];

On the other hand if you write it any other way then you might instantiate D F/Fs instead of RAM...You might want to look at Language Constructs in Xilinx ISE. Great place to know how to utilise the onchip inbuilt resources

Added after 1 minutes:

And what I understand the Synthesiser can only do it for you if its in the above format
 

what is distrubted ram

Yes, HDL syntax helps the synthesizer infer various structures. I suggested reading the chapter "HDL Coding Techniques" in the XST User Guide.

What is "Language Constructs"? I can't find it in the ISE 8 manuals.

In your example, if you define <reg_or_wire> to be registers, then you will probably get Block RAM instead of Distributed RAM. You can override that default behavior by applying the RAM_STYLE DISTRIBUTED constraint to the <ram_name> register array.
 

distributed rom

Well I use 7.1i so in there go to Edit->Language Constructs->VHDL/Verilog->Synthesis Constructs->Coding Examples. I am sure there will be a similar thing in 8.1

Here you will get lots of examples on how to use the various inbuilt resources like Block/Distributed Ram, Embedded Multipliers etc..with Verilog code which gets mapped into each. Only when u write ur code in that particular way the particular constructs get inferred.

And regarding the doubt whether it will synthesise to Block/Distributed RAM, if you use assign to read the data value outside of the always block then it will map to distributed ram and if u use an else part in always block i.e. when write enable is low,to read the ram,then it will synthesise to block ram. I suggest you use the Language Constructs. Great place with lots of examples.You can also find similar examples and lots more if you search xilinx website.For eg. **broken link removed**

And @echo47,regarding the DSP core problem I mailed you,please suggest something.
 

distributed ram

I found it under a different name in ISE Project Navigator 8.1.03i: Edit -> Language Templates -> Verilog -> Synthesis Constructs -> Coding Examples -> Distributed RAM.

The example is wrong (at least in ISE 8.1.03i). I chose resister inputs for the address and input data, added module inputs and outputs, and selected 4x4 memory size. ISE 8.1.03i generated Block RAM instead of Distributed RAM. No surprise, I've done this sort of thing before. I suggest using RAM_STYLE synthesis constraint to be sure you get what you want. The subtle HDL coding techniques sometimes change between compiler versions.
Code: 
module top (clk, we, myaddr, myidata, odata);
  parameter RAM_WIDTH = 4;
  parameter RAM_ADDR_BITS = 4;

  input clk, we;
  input [RAM_ADDR_BITS-1:0] myaddr;
  input [RAM_WIDTH-1:0] myidata;
  output [RAM_WIDTH-1:0] odata;

  reg [RAM_WIDTH-1:0] ram [(2**RAM_ADDR_BITS)-1:0];

  wire [RAM_WIDTH-1:0] odata;

  reg [RAM_ADDR_BITS-1:0] addr;
  reg [RAM_WIDTH-1:0] idata;

  always @(posedge clk) begin
    if (we)
      ram[addr] <= idata;
    addr <= myaddr;
    idata <= myidata;
  end

  assign odata = ram[addr];
endmodule
Thank you for reinforcing my determination to never use Project Navigator. ;)
 

parameterized distributed ram

Yes you are right, I synthesised it in 7.1 also and it mapped to Block RAM and then I changed the synthesis style to Distributed and lo, it mapped to Distributed RAM. Maybe Xilinx people should notice this,and one more thing can you specify this constraint for individual blocks,like suppose I want to instantiate a large RAM as distributed and a small one as block in order to conserve resources,can I do it then? Is it possible to specify individual synthesis attributes for each ?
 

distributed ram lut

The Xilinx docs and tools are peppered with small glitches like that. Xilinx is pretty good about fixing the big bugs. I think the glitches occur because the documentation is spread out over too many books, and probably difficult to maintain. You may want to keep a notebook describing your discoveries and workarounds, and then reread it occasionally.

Yes, you can apply RAM_STYLE DISTRIBUTED and RAM_STYLE BLOCK constraints independently to signals or globally to entire modules. However, I haven't yet found a way to instantiate two of the same modules, with one set to Distributed and the other set to Block. I've never really needed to do that, though.

In XST you can control each RAM independently by applying the constraint to the register array signal in your HDL:
Code: 
reg [RAM_WIDTH-1:0] ram [(2**RAM_ADDR_BITS)-1:0];  // synthesis attribute RAM_STYLE ram DISTRIBUTED;
Or you can constrain an entire module, thereby affecting all of its RAMs:
Code: 
module top (clk, we, myaddr, myidata, odata);  // synthesis attribute RAM_STYLE top DISTRIBUTED;
There may be other methods too.

The RAM_STYLE constraint should be described in your Constraints Guide, but beware - somewhere between ISE versions 7 and 8 Xilinx moved some of the constraint descriptions from the Constraints Guide to the XST User Guide. Why???
 

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