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How to design a low voltage current source?

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walker5678

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I am designing a low voltage current source, which need to work under 1.8V supply voltage, use standard 0.5um CMOS process.
Does the structure below satisfy the requirement? Can it work to generate a PTAT, and if it works, how to bias the amp ?
Appreciate your advice. Thanks.
Best regards,

17_1161594471.gif
 

Yes, the structure you show will generate a low voltage PTAT current. As for the Opamp, you can bias it from a separate const. gm core ( since it is the simplest to implement )
 

Hi elbadry
I konw that in the rail to rail input stage, there is constant gm structure, but how to use it to bias an amp? could you please describe it in more detail?

Thanks a lot.
 

fanrong said:
How about the effect of the offset of the OPAMP ?
Click to expand...

The offset affect the current very much. If no offset,

bias current = Delta(VBE)/R = VT*ln(n)/R,

With offset,

bias current = (VT*ln(n)+VOS)/R

if choose n=8, VOS ~ +/-5mV and VT=25mV in room temp,

bias current ~ (50+/-5)mV/R, which means 10% chip-to-chip variation.
 

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