More details about Tie-High and Tie-Low cells

tie-high and tie-low cells

Hello,


In the digital library, there are tie-high and tie-low cells. I know that the purpose of these cells is to provide ESD protections (avoid direct connection between gate and Power/Ground).

However, I would need more information about these cells :
- Is it mandatory to use such cells for all the signals tied to power/ground
or does it only apply in specific cases ? Which cases ?
- Is it usefull to use these cells for 0.25 or 0.18um technologies or is it only for
65/90nm processes ?
- What is the risk if I do not use tie high/low : process issues ? yield issue ?
ESD peak weakness ? ... ?
- Circuits already have ESD protections under pads. Isn't it enough to protect
signals inside the logic ?

Thanks for your help.
Regards,

Philippe.

tie-high tie-low cells

hi, I have seen the tie-high or tie-low cell used in compiled memory module wrapper for DFT. The port that they drive will be driven by test-related signals after DFT insertion.
the are not for ESD protection only.

tie high cell

Hi!!!

I think, what ESD protection is exist on MOS transistors in diode mode.
https://obrazki.elektroda.pl/86_1159810148.JPG

tie high net tie low

Give me a good reason NOT to use these pads to tieing signals high or low ?

Re: tie-high tie-low cells

Where and how the tied low/high cells should be inserted?

Should they be inserted in RTL?

Is there a special command for the synthesis tools to use such cells?

Thank you!

---------- Post added at 13:58 ---------- Previous post was at 13:52 ----------

So, what's purpose of the tie low/high cells? Finally, are they for ESD protection or not?

---------- Post added at 14:00 ---------- Previous post was at 13:58 ----------

Are these cells Pull-Ups and Pull-Downs?