Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

what delay statement won't be ignored for synthesis ? anyone

Status
Not open for further replies.
F

feel_on_on

Full Member level 5
Full Member level 5
Joined
Apr 29, 2005
Messages
283
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,298
Activity points
3,208
delay is ignored for synthesis

what delay statement won't be ignored for synthesis ? anyone tell me

WARNING: Xst :916-top.v line 528 : Delay is ignored for synthesis
statement as following :
PARAMETER TP =1;
temp_wb_ack_o_reg<=#Tp 1'b0

I have tried to use "SPECIFY ENDSPECIFY " ,but not synthesis.
pls tell me other method, Thanks a lot !
 

Hi,

Do you mean "why delay statement is ignored by Synthesis"?

A fix delay cannot be synthesised. Why? Because it is impossible. How do you construct that has, say, 10ns delay? The delay of a cell depends alot on process variation, voltage and temperature.

The solution is to have a state machine, or a hand-shake protocol to synchronise the events.

Regards,
Eng Han
 

Re: what delay statement won't be ignored for synthesis ? an

A delay statement cannot be used for synthesis because it uses gate/propogation delay to create the time delay and the number of gates can get large.
It will simulate fine though.
 

Re: what delay statement won't be ignored for synthesis ? an

Hi
to get certain dealy, I saw some people who instanciate buffer cells from standard cell library of the the target technology and use the delay of these buffers to get their required delay.
Disadvantage of this method is that you will need to re-calculate your delays if you change the technology.
So it will affect code portability and maintability.

Another way is to assure that all your dealys are multiples of clock cycle and just use FFs to get your sequentail delay

Thanks
Haytham
 

Re: what delay statement won't be ignored for synthesis ? an

All delays assigned in RTL will be ignored by synthesis tools.

delay value assigned in RTL has no effect on systhesis procedure.


best regards





feel_on_on said:
what delay statement won't be ignored for synthesis ? anyone tell me

WARNING: Xst :916-top.v line 528 : Delay is ignored for synthesis
statement as following :
PARAMETER TP =1;
temp_wb_ack_o_reg<=#Tp 1'b0

I have tried to use "SPECIFY ENDSPECIFY " ,but not synthesis.
pls tell me other method, Thanks a lot !
Click to expand...
 

Re: what delay statement won't be ignored for synthesis ? an

Few points here:

1. Actually, the delay of a 1 cm long wire is different from one technology to the other.
2. If delays are hard-coded in the RTL, its a wrong coding practice because delays could change. Such delays if specified in RTL will be only effective in simulations. Synthesis ignore it.
3. In case you still want to add delays... then you have to instantiate the delay cells rather than hard-coding as u have done. These will be synthesized.

Best Regards,
Harish
https://hdlplanet.tripod.com
https://groups.yahoo.com/group/hdlplanet
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top