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reading a file in testbench(verilog)

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verilog fread

hi all,
how to assign the input data written in a file to the port, for testbench purpose using verilog hdl?
suppose i have some samples of input data written in .dat file,
and in my testbench i want to input all the values written in that file, how can i do it?
i have tried in the below manner and could not find any data assigned to the input pin while simulating,

data_in = $fopen('' input.dat","r");

please help to solve this.........
 

verilog read file

$fopen will only open the file. To do any file operation in verilog this has to be done first. for reading from file try $memreadb (for binary files) or $memreadh (for hex files).

eg :
Code: 
reg [7:0] mem[1027:0];
......
initial
begin
  $readmemb("file_name",mem);
end

U also have $fscanf, $fgetc, $fread to read files. Not sure abt the exact syntax for their usage, but should be similar to above one.
 

    P

    param

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verilog file read

Here is the example ur looking for .....
Hope this helps
Code: 
module stim_gen (
   // Outputs
   clk, data
   );
   output clk;
   output [7:0] data;
   reg    clk;
   reg [7:0] data;
   integer   fd;
   integer   code, dummy;
   reg [8*10:1] str;
   
   initial begin
      fd = $fopen("_input.dat","r"); 
      clk = 0;
      data = 0;
      code = 1;
      $monitor("data = %x", data);
      while (code) begin
         code = $fgets(str, fd);
         dummy = $sscanf(str, "%x", data);
         @(posedge clk);
      end
      $finish;
   end // initial begin
   always #5 clk = ~clk;
endmodule // stim_gen

Contents of _input.dat file
Code: 
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
 
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reading a file in verilog

FYI,

If you want to process binary data, this can be tricky readmemb did not work for me when I needed to do this. I finally ended up using:

file = $fopen("code.vec", "r");


return_value = $fread( mem, file);
if (return_value !=1)
error = 1;
else
..............

"mem" is an eight bit varible. When the return_value is not 1, then the read failed and you are at the end of the file.

--- Steve
 

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    param

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Re: verilog file read

thanks for the example code nand gates....however i tried it and gave me errors so i tried making changes. Firstly for me an 'always' worked before the @(posedge clk) statement. Even after making this change it keeps giving me errors. Can someone please help me debug?
 

Hi all if any body implemented dwt image processing using verilog can u just send me the architecture and fsm design(if possible) or tell me how to start the coding part.please help me in that.
 

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