What is the best way to generate binary counter in Verilog?

module counter (clk, reset, count);
    input clk, reset;
    output [3:0] count;
    reg [3:0] count;
    always @(posedge clk or posedge reset )
         if (reset) 
              count <= 4'b0000;
         else
               count <= count + 1'b1;
endmodule

module bcd_count(clk, reset, ce, count);
   input clk, reset;
   input ce;  // count enable 
   output [7:0] count; // two digit bcd counter
   reg [7:0] count;

   always @(posedge clk or posedge reset) begin
      if (reset) begin
         count <= 7'h00;
      end else begin
         if (ce)
           if (count[3:0] == 9) begin
              count[3:0] <= 0;
              if (count[7:4] == 9)
                count[7:4] <= 0;
              else
                count[7:4] <= count[7:4] + 1;
           end else begin
              count[3:0] <= count[3:0] + 1;
           end
      end // else: !if(reset)
   end // always @ (posedge clk or posedge reset)
endmodule // bcd_count


module sven_seg (bcd, leds);
   input [3:0] bcd;
   output [6:0] leds;
   reg [6:0]   leds; 
   always @(bcd)
     case (bcd)  //abcdefg
       0: leds = 7'b1111110;
       1: leds = 7'b0110000;
       2: leds = 7'b1101101;
       3: leds = 7'b1111001;
       4: leds = 7'b0110011;
       5: leds = 7'b1011011;
       6: leds = 7'b1011111;
       7: leds = 7'b1110000;
       8: leds = 7'b1111111;
       9: leds = 7'b1111011;
       default: leds = 7'bx;
     endcase 
endmodule          


module top (
   // Outputs
   led0, led1, 
   // Inputs
   reset, clk, ce
   );
   input                ce;                     // To bcd_count of bcd_count.v
   input                clk;                    // To bcd_count of bcd_count.v
   input                reset;                  // To bcd_count of bcd_count.v

   output [6:0]         led0;                  // From bcd_count of bcd_count.v
   output [6:0]         led1;                   // From sven_seg0 of sven_seg.v, ...
   wire [7:0]  count;
   
   bcd_count bcd_count(
                       // Outputs
                       .count           (count[7:0]),
                       // Inputs
                       .clk             (clk),
                       .reset           (reset),
                       .ce              (ce));
   sven_seg sven_seg0 (
                       // Outputs
                       .leds            (led0[6:0]),
                       // Inputs
                       .bcd             (count[3:0]));
   sven_seg sven_seg1 (
                       // Outputs
                       .leds            (led1[6:0]),
                       // Inputs
                       .bcd             (count[7:4]));
   
endmodule // top