What causes LDO output ripples?

Hi Everyone,

I'm the beginner in the LDO design. I would like understand, what is actually causing the LDO output to have ripples when there is current load switching?

In my simulation test bench, I'm just placing a ideal current load to switch from 0 to 30mA periodically and load cap about 100pF connected to the output of LDO. There is output ripple about 200mVpp whenever the current switching. And when I increase the load cap to 1uF, the output ripples
reduced less than 20mV.

Please help me to understand this.

Thanks
Cheers.

- - - Updated - - -

chipdesign said:

Hi Everyone,

I'm the beginner in the LDO design. I would like understand, what is actually causing the LDO output to have ripples when there is current load switching?

In my simulation test bench, I'm just placing a ideal current load to switch from 0 to 30mA periodically and load cap about 100pF connected to the output of LDO. There is output ripple about 200mVpp whenever the current switching. And when I increase the load cap to 1uF, the output ripples
reduced less than 20mV.

Please help me to understand this.

Thanks
Cheers.

Click to expand...

I do understand the larger external cap suppress the ripples as Xc of the cap reduces providing
low impedance path to gnd for noise filtering. So, in the first place, I need to understand, in every LDO design, what is actually causing the output ripples? V=1R, I=the load current, so which "R" is that contributing to the voltage amplitude.

Thanks
Cheers.

The "R" you are asking for is the LDO output impedance. Rather than a simple resistance value, it's usually a frequency dependent complex impedance. It's mainly determined by the voltage regulator's feedback loop, you derive it in a circuit analysis. The output capacitor is connected in parallel to the existing regulator output impedance and (hopefully) reducing it in total.

In case of an unsuitably compensated regulator with inductive output impedance, the wrong capacitor value can worsen things or even cause oscillations.

Hi,

You know every LDO has a regulating power transistor (bjt or Mosfet).
(It is between LDO power input and LDO output)

It is regulating, in linear region, then you should know it has a resistance.
Increasing current will cause increasing voltage drop. This voltage drop causes decreasing output voltage.

Klaus

Hi guys,

Thanks for the replies. I have got better understanding now. So, basically the "R" I'm looking at is the effective output impedance of the LDO design, Effective Impedance = R||Xc.

R= RpassMOS||R1+R2 (resistor divider) Xc=load capacitance.
So, to reduce the output voltage drop, the effective output impedance to be reduced for the constant load current.
In the case, for smaller capacitor load, the R need to be small as well, which I believe some design techniques are
there to reduce output ripples.

Another thing, I'm attaching an example of LDO output ripple for a given Iload current transient.
Can you please explain the mechanism of it? What happen effectively when current load going from 0 to High and High to 0 in terms of output impedance with capacitor load on charging and discharging? I'm not there yet to understand that fully.

Thanks

R= RpassMOS||R1+R2 (resistor divider)

Click to expand...

Unlikely. Most LDOs, e.g. that producing the waveform in your post involve a feedback loop. The closed loop output impedance is considerably smaller than "RpassMOS" which is typically the high output resistance of a MOSFET in saturation mode. The oscillating nature of the waveform clarifies that the closed loop output impedance is involving a reactant (inductive) part.

FvM said:

Unlikely. Most LDOs, e.g. that producing the waveform in your post involve a feedback loop. The closed loop output impedance is considerably smaller than "RpassMOS" which is typically the high output resistance of a MOSFET in saturation mode. The oscillating nature of the waveform clarifies that the closed loop output impedance is involving a reactant (inductive) part.

Click to expand...

Hi FvM, are you saying that the undershoot and overshoot in the waveform are dominated by the closed loop impedance of the LDO? In the case of very large cap, say like 2-3uF, then the Xc of the cap dominating the close loop impedance?
Can you please make me understand how the external cap is involve in the undershoot and overshoot process? Really need your replies to make myself clear on this. Thanks

A large cap does not necessarily defeat the oscillations, it all depends on the LDO closed loop impedance.

To discuss a simple case, have an output stage with pure resistive output impedance. Then add a feedback loop with first order low-pass characteristic (single pole) and get a partly inductive output impedance. There are different options to make it stable:

- make the cap very large so that there's no resonance in the frequency range of inductive output impedance (probably unsuitable)

- make the feedback gain very low (mostly unwanted)

- use a capacitor with high ESR (e.g. electrolytic) to reduce the resonance Q (typical design approach with old fashion voltage regulators)

-tailor the feedback compensation for stability with low esr caps in a suitable capacitance range (modern LDO)

You obviously need to deepen your knowledge in circuit analysis and feedback systems.

Hi FvM,

Thanks for the explanation indeed. Yes, I will further enlighten my knowledge in the both area that you suggested.

Thanks

What you show in the picture is not "ripple" as a power supply
designer would use the term. They are overshoot / undershoot
and they come from the finite response time of the regulator
and (if they persist more than a half-cycle) an inadequately
tuned feedback loop.

No LDO can eliminate the excursions. A well designed combo
of good output filter caps and correspondingly-tuned (because
the output filter does affect the feedback loop, a shunt term)
feedback network can minimize the load-step perturbation to
an acceptable level (ideally, within the required regulation
band of whatever's being powered).

Don't expect to eliminate it altogether, that is endless work
and will never entirely happen. Go at it from requirements
and what's tolerable. You may still have some trouble if
expectations and technology are not compatible (like a
10nS settling time in a 40V technology, nuh-uh).

Hi Freebird,

Thanks for replying it as well. I did some study on the presence of undershoot and overshoot of the LDO, it seems the very high closed loop feedback bandwidth/infinite bandwidth system will have least effect of it at the LDO output, but in reality due to finite bandwidth response time, the overshoot and undershoot will present. The problem now is, I'm planning on a "capacitor free LDO", thus I can't depend on the large external cap for the undershoot/overshoot filtering.

Recently, i saw some papers written about techniques for undershoot /overshoot reduction without depending on large load external cap..hopefully will get some idea on it. If you have any suggestion please let me know.

If you look carefully at the cap-free LDOs you will find that
their overshoot specs (if any) are tied to an input voltage
step or an output load current step whose characteristic
frequency (like 1/t_rise) is lower than the loop bandwidth.
Which is fine as long as it's realistic, but many applications
can impose faster load steps than these regulators on their
own (i.e. with "zero" capacitance) can truly handle. It's a
marketing play in large part, getting people to spend money
on your IC instead of somebody else's capacitors.

Capacitor quality matters as much, maybe more, than size.
Specifically ESR & ESL. You may not need the caps that
remain, to hold up for long (depends on loop BW) but you
would like them to hold up well for that period, and ESR
makes for a pedestal jump while ESL makes the cap slow
to do its part initially.

Challenge any idea that you should, or even would benefit
significantly from, eliminating 1 or N capacitors. Presumably
your load devices will still have close-in decoupling per
best practices, so there's a minimum pool of filtering cap
regardless. Then, what's (say) two more, big and little
high-Q ceramics? Also there is a minimum ESR/ESL for
some LDOs to obtain stable operation, need a HF zero to
keep the poles in check.

Again, since the overshoots will always be present, you
need to quantify what's acceptable, and add design margin,
and work to that.