Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Can drain and source be reversed in FETs?

Status
Not open for further replies.
I

irfansyah

Advanced Member level 4
Full Member level 1
Joined
Dec 29, 2004
Messages
106
Helped
9
Reputation
18
Reaction score
1
Trophy points
1,298
Location
New South Wales
Activity points
1,124
My friends and i have some kind of debate. We argue on whether drain and source in FETs are reversible.

Which is correct? Can it be reversed? Please explain your arguments, guys :D
 

In some BJT transistors you can revers Emitter with Collector and it will function in the reversed configuration (β is very low).
FET transistor channel resistance is controlled by Ugs(gate-source) and not by Gate-Drain .. conclusion: source and drain can not be reversed ..
 

it all depends upon the geometry. If it is double diffused, the doping is not symmetrical. Very old symmetrical ones may be reversible. On most JFETs the doping profiles are symmetrical, so they are reversible. One thing is that transistors are tested in the ordinary configuration. There is a chance they will not meet all specifications in the reverse direction.
 

i would disagree.

if it is cmos, drain and gate makes no difference. if you try to extract a layout into spice format, they couldnt tell the difference between a drain and a source.

it is totally symetrical. what makes it source and what makes it drain is just the connections you put to it.

i'm not that sure about jfets though.
 

The drain and source are interchangeable. One way is to use a P-fet in the power line to protect the circuit from wrong polairity, the other way is protection to prevent battery voltage going out of the circuit.
But don't forget the diode between the D and S: one way it will conduct anyway! turning the gate on will lower the Uds (0.7V) to Rds-on*I
 

we are talking JFETS or MOSFETS here could someone clarify.
I see discussions on both
 

see its schematic symbol, if there is arrow then you cant reverse any connnections, if not then you can reverse things.

anyway:

In bjt its a must to follow the collector-emitter order and they cant be reversed due to different doping.


In jfet its reversable

In IGFET its non reversable since the source and the transistor substrate are physically connected, and thats why there is an arrow in its schematic symbol
 

the condition for FET is it should be reverse biased in forward direction.but source and drain can be connected as u like bcos sorce and drain are single substrate
and my point is it should highly doped (drain and source)
 

Oh ! That's a simple win to one whoi says yes they can be reversed !

Want a proof !
Just Download the data sheet of N type JFET 2N5484 , it clearly specifies that reversing drain and source can be done !

But ..then this does not apply to every JFET ! you must check datasheets for that.

So who wins finally !! None of you !!!
Congrats !
 

Apart from application side,I want to know about the reversal in Device Modelling prospective.So can any one explain about why the reversal of drain and source of the specified components TN5485 is possible?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top