Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Of course. If you use +notimingcheck option, when there are setup/hold/timing
happened in your FF, you will not got an "X" (notifier assertion in gate level verilog
library) and warning messages.
My opinion is you should better use +no_notifier instead, which will report setup/hold
time violation but will not change your FF's output into "X", which is good for running gate level design having multiple clock domains.
for simulaitn on gate-level without SDF file, you should with +notimingcheck.
for post-apr simulaiton with SDF file, you should don't with +notimingcheck,
otherwise the simulation should be non-meaningful.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
