hannachifaten
Member level 2
Hi every body ,
i try to use the MIG to Write and Read from DDR3 , i want to communicate my spartn 6 to DDR3 , i have used core generator Memory Interface Genrator( it generate output files in User Design and Example Design ), i choose begin with the example design using the traffic generator BUT :???: my worries are how to modify the Traffic genrator's file ( test bench ...) to write and read my own words ,
- i have done the first step that i'm tring to change the data_Mode to fixed mode , and i put only one word into " fixed_data_input"
after that i don't know how i can modify this last one to read and write different DATA , Don't forget i'm a begnner in VHDL and FPGA , i'm trainee :sad:
ANY HELP PLEASE ? :???:
i try to use the MIG to Write and Read from DDR3 , i want to communicate my spartn 6 to DDR3 , i have used core generator Memory Interface Genrator( it generate output files in User Design and Example Design ), i choose begin with the example design using the traffic generator BUT :???: my worries are how to modify the Traffic genrator's file ( test bench ...) to write and read my own words ,
- i have done the first step that i'm tring to change the data_Mode to fixed mode , and i put only one word into " fixed_data_input"
after that i don't know how i can modify this last one to read and write different DATA , Don't forget i'm a begnner in VHDL and FPGA , i'm trainee :sad:
ANY HELP PLEASE ? :???: