[SOLVED] Problem with simulating 8bit LFSR in HSPICE

Hello all,

I want to simulate 8bit LFSR in HSPICE . The following is the code that I have written :

.include technology_file.sp
**************************************************************************
**** Parameters
**************************************************************************
.param SUPPLY = 5
.param wp = 1.4u
.param wn = 0.7u
.param lp = 0.2u
.param ln = 0.2u
**************************************************************************
**** Constant Voltage Sources
**************************************************************************
Vdd vdd GND SUPPLY
Gnd GND 0 0

VCLK CLK GND PULSE (SUPPLY GND 0 0.005n 0.005n 0.995 2n)

**************************************************************************
**** Subcircuit Dictionary
**************************************************************************
.SUBCKT XOR2 input1 input2 output VDD GND

M1 wire1 input1 VDD VDD tsmc18P w=wp l=lp
M2 wire2 input2 VDD VDD tsmc18P w=wp l=lp

M3 wire1 input1 GND GND tsmc18N w=wn l=ln
M4 wire2 input2 GND GND tsmc18N w=wn l=ln

M5 output input1 wire3 VDD tsmc18P w=wp l=lp
M6 wire3 wire2 VDD VDD tsmc18P w=wp l=lp
M7 output wire1 wire4 VDD tsmc18P w=wp l=lp
M8 wire4 input2 VDD VDD tsmc18P w=wp l=lp

M9 output input1 wire5 GND tsmc18N w=wn l=ln
M10 wire5 input2 GND GND tsmc18N w=wn l=ln
M11 output wire1 wire6 GND tsmc18N w=wn l=ln
M12 wire6 wire2 GND GND tsmc18N w=wn l=ln

.ENDS XOR2


.SUBCKT DFF_1 D R Q CLK VDD GND

M0_D Q 2 GND GND tsmc18N w=0.7u l=0.2u
M1_D 2 3 GND GND tsmc18N w=0.7u l=0.2u
M2_D 4 CLK GND GND tsmc18N w=0.7u l=0.2u
M3_D 3 R GND GND tsmc18N w=0.7u l=0.2u
M4_D 5 D GND GND tsmc18N w=0.7u l=0.2u
M5_D 6 7 GND GND tsmc18N w=0.7u l=0.2u
M6_D 3 4 6 GND tsmc18N w=0.7u l=0.2u
M7_D 7 CLK 5 GND tsmc18N w=0.7u l=0.2u
M8_D Q 2 VDD VDD tsmc18P w=1.2u l=0.2u
M9_D 2 3 VDD VDD tsmc18P w=1.2u l=0.2u
M10_D 4 CLK VDD VDD tsmc18P w=1.2u l=0.2u
M11_D 8 D VDD VDD tsmc18P w=1.2u l=0.2u
M12_D 3 R 9 VDD tsmc18P w=1.2u l=0.2u
M13_D 9 CLK 10 VDD tsmc18P w=1.2u l=0.2u
M14_D 10 7 VDD VDD tsmc18P w=1.2u l=0.2u
M15_D 7 4 8 VDD tsmc18P w=1.2u l=0.2u

.ENDS DFF_1


.SUBCKT EIGHT_BIT_LFSR CLK OUTPUT VDD GND

XDFF0 D0 R Q0 CLK VDD GND dff_1 lp=lp ln=ln
XDFF1 Q0 R Q1 CLK VDD GND dff_1 lp=lp ln=ln
XDFF2 Q1 R Q2 CLK VDD GND dff_1 lp=lp ln=ln
XDFF3 Q2 R Q3 CLK VDD GND dff_1 lp=lp ln=ln
XDFF4 Q3 R Q4 CLK VDD GND dff_1 lp=lp ln=ln
XDFF5 Q4 R Q5 CLK VDD GND dff_1 lp=lp ln=ln
XDFF6 Q5 R Q6 CLK VDD GND dff_1 lp=lp ln=ln
XDFF7 Q6 R Q7 CLK VDD GND dff_1 lp=lp ln=ln

XEXOR_A Q1 Q2 output_A VDD GND xor2 lp=lp ln=ln
XEXOR_B Q3 Q7 output_B VDD GND xor2 lp=lp ln=ln
XEXOR_C output_A output_B D0 VDD GND xor2 lp=lp ln=ln

.ENDS EIGHT_BIT_LFSR
*******************************************************************************
**** Instance Section
*******************************************************************************
XU811 U811:CLK U811:OUTPUT U811:VDD U811:GND eight_bit_LFSR

**************************************************************************
**** AC Analysis
**************************************************************************
*.option post probe
*.probe V(VDD*) V(OUTPUT*) V(CLK*) I(VDD*)
.tran 100n 20us
.END




While I am running this in Hspice : I keep on getting errors like
_______________________________________________________________________________________
ERROR:
**************************************************************************
.subckt xor2 input1 input2 output vdd gnd

**error** .ends card missing at readin

>error ***difficulty in reading input
_________________________________________________________________________________________

Can anyone suggest me something to run this successfully ? Have I done something wrong in the way subcircuits are defined ?


Thanking in anticipation

Re: HSPICE Code of 8 bit LFSR

I am not sure about the specific error message you are getting but one thing that doesn't look right:

Gnd GND 0 0

is invalid. I assume you mean something like:

Vgnd GND 0 0

Your node "R" in the SUBCKT EIGHT_BIT_LFSR doesn't seem to be driven by anything so will cause convergence problems. I guess you intend to connect that somewhere.

Keith

- - - Updated - - -

Just to add, I would have expected the subcircuit call

XU811 U811:CLK U811:OUTPUT U811:VDD U811:GND eight_bit_LFSR

to simply have been:

XU811 CLK OUTPUT VDD GND eight_bit_LFSR

Re: HSPICE Code of 8 bit LFSR

Keith ,

The job concluded with just this change itself -Vgnd GND 0 0.
Cant believe I made such a stupid mistake :wink:
Thank you very much

Re: HSPICE Code of 8 bit LFSR

Hello ,

I am facing few problems yet with the simulation of this 8 bit LFSR (figure attached )and I am guessing its because of the way the 8 bit LFSR is getting instantiated.

Can anyone tell me what could be the reason behind the clock pulse getting generated and being seen externally through signal V(CLK) but I dont see the same clock signal across the V(CLK) within subcircuit 8 bit LFSR ?

Also is something wrong with the way I define my power supplies VDD and GND ? I dont even see those values in my instantiation of 8 bit LFSR ?


PS- If anyone has any such decent small sized sequential SPICE deck and can share here it will be highly appreciated.


Thanking in anticipation
Shaival

*
8 bit LFSR Reference - https://www.google.com/imgres?um=1&...w=176&start=0&ndsp=18&ved=1t:429,r:4,s:0,i:85

Vdd vdd GND SUPPLY
change to VDD VDD GND SUPPLY

maintain caps for VDD and GND all over the code