help me to write a VERILOG code for MODULO 12 counter

`define TICK #2
module mod13Cntr(clk, reset, Q);
input clk, reset;
output [3:0] Q;
reg [3:0] Q;

//Behavioral Code for a Mod-13 counter
always @ (posedge clk) begin
    if (~reset) begin
        if (Q == 4'b1100) begin
           Q <= `TICK 4'b0;
       end
       else begin
           Q <= `TICK Q+1;
       end
    end
end
always @ (posedge reset) begin
    Q <= 4'b0000;
end
endmodule

module mod_n_cntr #(parameter [3:0] n = 'd12)(
           input clk_i, rst_n_i,
           output [3:0] cntr_o);

   reg [3:0] cntr_d, cntr_q;


always @ (posedge clk_i, negedge rst_n_i) begin: clk process
    if (!rst_n_i) begin
       cntr_q <= 'b0;
    end else begin
       cntr_q <= cntr_d;
    end
end

always @ (*) begin : comb
   if(cntr_q == n - 1) begin
       cntr_d = 'b0;
   end else begin
       cntr_d = cntr_q + 1;
   end
end

assign cntr_o = cntr_q;

endmodule