[URW]
Newbie level 3
Hello all, nice to see an active FPGA Forum here.
I am involved in a Spartan 6 prototype design involving an I2C Master Core. It is a well proven core that is thankfully shared on OpenCores.org. My design involves this single Master controlling 4 I2C slave devices, 3 are identical frequency synthesizers, the last I2C controlled device is a video IC (registers only).
My question is: How does the master core go about assigning addresses, and communicating with each of the freq. synth's individually? In the beginning won't all IC's respond back at the same time?
I am involved in a Spartan 6 prototype design involving an I2C Master Core. It is a well proven core that is thankfully shared on OpenCores.org. My design involves this single Master controlling 4 I2C slave devices, 3 are identical frequency synthesizers, the last I2C controlled device is a video IC (registers only).
My question is: How does the master core go about assigning addresses, and communicating with each of the freq. synth's individually? In the beginning won't all IC's respond back at the same time?