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Slew Rate of an MDAC stage in pipelined ADC!

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chandra3789

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frnds i am simulating MDAC stage in pipelined ADC........

The output waveform is shown below......


The DAC's functionality is working fine but when you have a close look at the output waveform you can see the negative and positive slopes of the output waveform.
The time of reaching the final value is divided as slewing time and settling time.......
if you observe the positive slewing is quite proper and there are no problems with it.....but the negative slope output is not slewing properly i.e., the slope is not a constant....because of this the negative output is a bit erroneous and the error is unacceptable......
so please tell me why the negative slewing is not proper ? what could be the reason for it?
 

Looks like the bottom has an RC characteristic (like a current sink that's run
out of headroom and gone low impedance) while the top has a constant-current
characteristic. But I question whether one is any better than the other if they
both settle to minimum error before next clock edge.
 
hello dick_feebird.......
sir,

The problem is the negative slope output is not settling to the desired accuracy within the desired time .......according to slew rate and the positive slope output the output should settle to 0.1% accuracy of its final value within 5ns...the positive slope output is working fine but because of this RC kind of characteristic the negative slope output is taking very long time to settle.....
i tried by interchanging the inputs , even in that case the positive slope output is working properly but the other one is improper.....
plz help me.....
 

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