samviva72
Newbie level 5
This is my first post and I am about to ask a very very basic question. I have never touched Verilog before nor any other HDLs, but I know C, C++ etc. Can somebody please give me the equivalent of the following C code in Verilog (if such thing exists)? I want to be able to define and populate the array within a verilog module itself, and it is just for simulation purposes.
I would be very grateful if somebody can give me the code, then I will use this as a basis to start learning more about verilog.
}
I would be very grateful if somebody can give me the code, then I will use this as a basis to start learning more about verilog.
Code:
void main(void)
{
int array_1[] = {1, 2, 3, 4};
int array_2[] = {5, 5, 5, 5};
int i;
int c_sum = 0;
for(i=0; i<4; i++)
{
c_sum = c_sum + (array_1[i]*array_2[i]);
}
}