The feedback resistor on a CMOS inverter

I would to know:
How the feedback resistor used with a CMOS inverter (working as an amplifier) bias the inverter to Vdd/2. An equation explaining this would be great.
How can I calculate the gain of this amplifier?
If I connect also a resistor ( R) to the inverter's input this would make the gain -Rf/R? (like an op amp inverter configuration)

Thanks in advance

It biases the inverter to the position of equal drain
currents, NMOS vs PMOS. This is unlikely to be exactly
VDD/2 (a matched resistor would be closer; NMOS vs
PMOS, there's nothing that says so).

This structure will bias the inverter or slaves at the
point of maximum sensitivity, which is useful.

However a inverter biased so, will tend to have a low
stage gain because both devices are at the border
between linear & saturation, well above VT, so gm is
well below peak and Zout sucks. It is nothing close to
an ideal op amp. But it is as cheap a shot as you can
get.

neonwarrior said:

... If I connect also a resistor ( R) to the inverter's input this would make the gain -Rf/R? (like an op amp inverter configuration)

Click to expand...

If you consider the low gain (order of -10) of a single inverter stage - s. also dick_freebird's answer above - a lower gain (e.g. -2, -3, or -5) can surely be attained by such a configuration.

I believe, that some comments are appropriate:
* For two ideal complementary transistors the transition from high (VDD) to low output level occurs at a common input voltage of VDD/2. The midpoint of this "quasi-linear" transition region also is at VDD/2. Therefore, a feedback resistor Rf between output and common input creates the correct bias (which is dc stable because of the negative feedback action).
* However, when the common input node is connected (via a capacitor) to a signal voltage the feedback resistor Rf also acts as a load resistor. Since the MOS pair acts as a current source, the load resistor determines the voltage gain of the whole circuit. Therefore, with an Rf value in the order of - let's say - 100 kohms you easily can get a gain of 100...500.
* Since this gain value is strongly dependent on MOS parameters it makes sense to apply signal feedback. For this purpose the input signal is applied through a series Rin-Cin combination. Then, the resulting gain is app. Rf/Rin. For this combination, stable gain values of 10..20 are not uncommon.

Added later: The CMOS pair acts (in principle) as a current source because resp. if the internal MOS output resistance is neglected.

hiiiiii LvW..

i need to know about self biased inverter ( output node ir drain of PMOS and NMOS is connected to Common Gate via a resistor) , i have gone through some paper in which they are using that as a buffer amplifer and according to paper self biased inverter reduces second harmonics.
thing i want to know is how this circuit works and how it reduces the second harmonics.

basically i am working on Power amplifer design for 402-405 MHz and power amplifer should deliver 500uwatt power to 50 ohm load.
i have attached the circuit diagram.please check that one and plzzz reply...