krishanu007
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I want a synthesizable clock generator code in verilog.
please dont give me always #delay clk = ~clk
& dont tell me to search google for PLL..
give me material (picture or block diagram or explanation of code) of how its done.:grin:??
please dont give me always #delay clk = ~clk
& dont tell me to search google for PLL..
give me material (picture or block diagram or explanation of code) of how its done.:grin:??