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VHDL Programming, define a specific variable

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karan1207

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please can you suggest how in VHDL I can define a variable which is visible in multiple processes of different components,, for example, I need a common CLK
 

Re: VHDL Programming

For every component, you will define a clock input.
When you connect blocks, you will connect the same clock signal for every block.
--
Amr Ali
 

Re: VHDL Programming

I have defined aclock input for every component, but how do i connect the clk. could u elaborate please. do i need to define the variable clk in the main program as global. how to do it?
 

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